PIC16F87-E/P Microchip Technology, PIC16F87-E/P Datasheet - Page 278

• Manufacturer Part Number: PIC16F87-E/P
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F87-E/P

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: SSP, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 22.86 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PICmicro MID-RANGE MCU FAMILY
17.1
SPI is a trademark of Motorola Corporation.
I
DS31017A-page 17-2
2
C is a trademark of Philips Corporation.
Introduction
The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicat-
ing with other peripheral or microcontroller devices. These peripheral devices may be serial
EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate
in one of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I
Figure 17-1
the block diagrams for the two different I
Figure 17-1:
- Full Master Mode
- Slave mode (with general address call)
shows a block diagram for the SPI mode, while
SPI Mode Block Diagram
SDO
SCK
SDI
SS
2
C™)
Preliminary
Read
SS Control
SMP:CKE
Select
Edge
Enable
bit0
Select
2
Edge
C modes of operation.
SSPBUF reg
Data to TX/RX in SSPSR
TRIS bit
2
SSPM3:SSPM0
SSPSR reg
Clock Select
4
2
shift clock
Prescaler
Write
4, 16, 64
Figure
TMR2 output
data bus
Internal
2
1997 Microchip Technology Inc.
17-2, and
T
OSC
Figure 17-3
show