PIC16F870-E/SO Microchip Technology, PIC16F870-E/SO Datasheet - Page 99
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PIC16F870-E/SO
Manufacturer Part Number
PIC16F870-E/SO
Description
28 PIN, 3.5KB ENH FLASH, 128 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F870-ISO.pdf
(172 pages)
4.PIC16F870-ISO.pdf
(6 pages)
Specifications of PIC16F870-E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB16F871 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F870-ISO PDF datasheet #3
- PIC16F870-ISO PDF datasheet #4
- Current page: 99 of 172
- Download datasheet (4Mb)
FIGURE 11-9:
11.10.1
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit, GIE, decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.13 for details on SLEEP
mode.
2003 Microchip Technology Inc.
The following table shows which devices have which interrupts.
PIC18F870
PIC18F871
PSPIF
PSPIE
Device
EEIF
EEIE
on
INT INTERRUPT
TMR1IF
TMR1IE
ADIF
ADIE
the
T0IF
Yes
Yes
TMR2IF
TMR2IE
RB0/INT
RCIF
RCIE
INTERRUPT LOGIC
CCP1IF
CCP1IE
INTF
Yes
Yes
TXIF
TXIE
pin,
RBIF
Yes
Yes
flag
bit
PSPIF
Yes
—
INTF
ADIF
Yes
Yes
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
RCIF
Yes
Yes
11.10.2
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 5.0).
11.10.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 4.2).
TXIF
Yes
Yes
TMR0 INTERRUPT
PORTB INTCON CHANGE
CCP1IF
PIC16F870/871
Yes
Yes
00h) in the TMR0 register will set
TMR2IF
Yes
Yes
Wake-up (If in SLEEP mode)
TMR1IF
Interrupt to CPU
DS30569B-page 97
Yes
Yes
EEIF
Yes
Yes
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