PIC16F873A-E/ML Microchip Technology, PIC16F873A-E/ML Datasheet - Page 280
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F873A-E/ML
Manufacturer Part Number
PIC16F873A-E/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873A-ISO.pdf
(234 pages)
4.PIC16F873A-ISO.pdf
(6 pages)
5.PIC16F873A-ISO.pdf
(4 pages)
6.PIC16F873A-ISO.pdf
(6 pages)
7.PIC16F873A-ISO.pdf
(4 pages)
8.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F873A-E/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873A-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- Current page: 280 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.2
DS31017A-page 17-4
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Control Register
Register 17-1:
bit 7
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit
(I
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next start bit, stop bit, or not ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress.
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
2
2
R/W-0
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
SMP
2
2
2
Or’ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the SSP is
in IDLE mode.
C master or slave mode:
C slave mode:
C master mode:
R/W-0
CKE
SSPSTAT: SSP Status Register
2
C mode only)
Preliminary
D/A
R-0
2
C mode only)
2
C mode only)
R-0
P
R-0
S
R/W
R-0
1997 Microchip Technology Inc.
R-0
UA
bit 0
R-0
BF
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