PIC16F876-04E/SP Microchip Technology, PIC16F876-04E/SP Datasheet - Page 659
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F876-04E/SP
Manufacturer Part Number
PIC16F876-04E/SP
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F876-04E/SP
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F87604E/SP
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 659 of 688
- Download datasheet (3Mb)
Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
Combined format:
S
(Code + A9:A8)
Slave Address
From slave to master
From master to slave
Slave Address R/W A Data A/A Sr
(write)
(read)
R/W A
data to this slave and reads data from this slave.
When a master does not wish to relinquish the bus (which occurs by generating a STOP condi-
tion), a repeated START condition (Sr) must be generated. This condition is identical to the start
condition (SDA goes high-to-low while SCL is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to send “commands” to the slave and then
receive the requested information or to address a different slave device. This sequence is shown
in
Figure A-8:
Figure
Slave Address
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(A7:A0)
A-8.
Sr = repeated
Start Condition
(n bytes + acknowledge)
(read or write)
Combined Format
Slave Address R/W A Data A/A
A
Data
A
(write)
Data A/A
Direction of transfer
may change at this point
Sr Slave Address
(Code + A9:A8)
P
(read)
Appendix A
R/W A Data A
DS31034A-page 34-7
Data
A P
34
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