PIC16F876AT-I/ML Microchip Technology, PIC16F876AT-I/ML Datasheet - Page 36
![28 PIN, 14KB ENH FLASH, 368 RAM, 22 I/O,](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F876AT-I/ML
Manufacturer Part Number
PIC16F876AT-I/ML
Description
28 PIN, 14KB ENH FLASH, 368 RAM, 22 I/O,
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F876AT-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 36 of 234
- Download datasheet (5Mb)
PIC16F87XA
REGISTER 3-1:
DS39582B-page 34
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER (ADDRESS 18Ch)
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
Unimplemented: Read as ‘0’
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read; RD is cleared in hardware. The RD bit can only be set (not
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
- n = Value at POR
EEPGD
R/W-x
bit 7
operation)
can only be set (not cleared) in software.
cleared) in software.
U-0
—
U-0
—
W = Writable bit
‘1’ = Bit is set
U-0
—
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WREN
R/W-0
2003 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
bit 0
RD
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