PIC16F946-E/PT Microchip Technology, PIC16F946-E/PT Datasheet - Page 206

• Manufacturer Part Number: PIC16F946-E/PT
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F946-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 336 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SSP, I2C, AUSART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, MA160011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA160011 - DAUGHTER BOARD PICDEM LCD 16F91X
• Lead Free Status / Rohs Status: Details

PIC16F946
FIGURE 16-8:
TABLE 16-6:
DS41265A-page 204
Addr
0Bh,
8Bh
0Ch
0Dh
8Ch
8Dh
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Instruction Flow
OSC1
CLKO
GIE bit
(INTCON<7>)
PC
Instruction
Fetched
Note 1:
INT pin
INTF Flag
(INTCON<1>)
Instruction
Executed
(3)
INTCON
2:
3:
4:
5:
Name
PIR1
PIR2
PIE1
PIE2
Shaded cells are not used by the interrupt module.
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 T
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
CLKO is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
SUMMARY OF INTERRUPT REGISTERS
OSFIF
OSFIE C2IE
Q1
EEIE
Bit 7
EEIF
GIE
Inst (PC - 1)
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
ADIE
PEIE
ADIF
Bit 6
C2IF
Q3
(4)
Q4
(5)
RCIF
RCIE
C1IE
Bit 5
T0IE
C1IF
Q1
Inst (PC + 1)
Inst (PC)
Q2
(1)
LCDIF
LCDIE
Bit 4
INTE
TXIF
TXIE
PC + 1
CY
Q3
. Synchronous latency = 3 T
Preliminary
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIF
RBIE
Bit 3
Q4
—
—
Interrupt Latency
Q1
Dummy Cycle
CCP1IF
LVDIE
LVDIF
Bit 2
T0IF
Q2
PC + 1
—
Q3
TMR2IF TMR1IF 0000 0000 0000 0000
Q4
(2)
Bit 1
INTF
—
—
CY
, where T
Q1
Dummy Cycle
Inst (0004h)
CCP2IF 0000 -0-0 0000 -0-0
CCP2IE 0000 -0-0 0000 -0-0
Q2
Bit 0
RBIF
0004h
CY
Q3
© 2005 Microchip Technology Inc.
= instruction cycle time.
0000 000x 0000 000x
POR, BOR
Q4
Value on
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Value on
all other
Q3
Resets
Q4