PIC16LF819T-I/MLTSL Microchip Technology, PIC16LF819T-I/MLTSL Datasheet - Page 211
PIC16LF819T-I/MLTSL
Manufacturer Part Number
PIC16LF819T-I/MLTSL
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F818-ISO.pdf
(8 pages)
4.PIC16F818-ISO.pdf
(8 pages)
5.PIC18F2450-ISO.pdf
(324 pages)
Specifications of PIC16LF819T-I/MLTSL
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16LF819TIMLTSL
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC18F2450-ISO PDF datasheet #5
- Current page: 211 of 324
- Download datasheet (6Mb)
18.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPx bits have no direct
effect. CPx bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTx Configuration bit is ‘0’. The EBTRx
bits control table reads. For a block of user memory
with the EBTRx bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 18-6:
© 2008 Microchip Technology Inc.
Results: All table writes disabled to Blockn whenever WRTx = 0.
TBLPTR = 0008FFh
Register Values
PC = 001FFEh
PROGRAM MEMORY
CODE PROTECTION
TABLE WRITE (WRTx) DISALLOWED
Program Memory
TBLWT*
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figure 18-6 through Figure 18-8
illustrate table write and table read protection.
Note:
000000h
0007FFh
000FFFh
001000h
001FFFh
002000h
003FFFh
PIC18F2450/4450
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
Chip Erase or Block Erase function. The
full Chip Erase and Block Erase functions
can only be initiated via ICSP operation or
an external programmer.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
DS39760D-page 209
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