PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 222
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 222 of 320
- Download datasheet (6Mb)
PIC18C601/801
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS39541A-page 222
Before Instruction
After Instruction
Decode
C
REG
WREG
N
OV
DC
Z
C
REG
WREG
N
OV
DC
Z
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ’f’
ADD WREG and Carry bit to f
[ label ] ADDWFC
0
d
a
(WREG) + (f) + (C)
N,OV, C, DC, Z
Add WREG, the Carry Flag and data
memory location ’f’. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in data memory
location 'f'. If ’a’ is 0, the Access Bank
will be selected. If ’a’ is 1, the Bank
will be selected as per the BSR value.
1
1
ADDWFC
Read
Q2
0010
1
02h
4Dh
?
?
?
?
0
02h
50h
0
0
0
0
f
[0,1]
[0,1]
255
00da
REG, W
Process
Data
Q3
ffff
f [,d [,a]]
dest
destination
Advance Information
Write to
Q4
ffff
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
N
Z
WREG
N
Z
Q1
Read literal
=
=
=
=
=
=
AND literal with WREG
[ label ] ANDLW
0
(WREG) .AND. k
N,Z
The contents of WREG are AND’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
1
1
ANDLW
0000
Q2
’k’
0A3h
?
?
03h
0
0
k
2001 Microchip Technology Inc.
255
1011
5Fh
Process
Data
Q3
k
kkkk
WREG
Write to
WREG
Q4
kkkk
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