PIC18F1330T-I/SO Microchip Technology, PIC18F1330T-I/SO Datasheet - Page 24

• Manufacturer Part Number: PIC18F1330T-I/SO
• Description: 8KB, Flash, 256bytes-RAM, 16I/O, 8-bit Family,nanoWatt,MotorControl 18 SOIC .300
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1330T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F1330T-I/SOTR

PIC18F1230/1330
FIGURE 4-4:
4.5
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register). The result may then be immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Section 4.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
4.6
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’.
Therefore, Blank Checking a device merely means to
verify that all bytes read as FFh except the
Configuration bits. Unused (reserved) Configuration
bits will read ‘0’ (programmed). Refer to Table 5-1 for
blank configuration expect data for the various
PIC18F1230/1330 devices.
DS39752B-page 24
PGC
PGD
Verify Data EEPROM
Blank Check
1
0
2
1
3
0
SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
4
0
P5
PGD = Input
1
2
3
4
5
6
7
8
P6
9
LSb
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 “Read Data EEPROM Memory” and
Section 4.2 “Verify Code Memory and ID Locations”
for implementation details.
FIGURE 4-5:
P14
10
1
11
2
PGD = Output
Blank Check Device
12
Shift Data Out
3
13
4
blank?
device
Abort
Start
14
Is
5
No
15
6
BLANK CHECK FLOW
© 2009 Microchip Technology Inc.
16
MSb
P5A
Yes
Fetch Next 4-Bit Command
1
n
PGD = Input
2
Continue
n
3
n
4
n