PIC18F2431T-I/MM Microchip Technology, PIC18F2431T-I/MM Datasheet - Page 153
PIC18F2431T-I/MM
Manufacturer Part Number
PIC18F2431T-I/MM
Description
16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18F2431T-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4431 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2431T-I/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- Current page: 153 of 392
- Download datasheet (4Mb)
17.1
The Input Capture (IC) submodule implements the
following features:
• Three channels of independent input capture
• Edge-Trigger, Period or Pulse-Width
• Programmable prescaler on every input capture
• Special Event Trigger output (IC1 only)
• Selectable noise filters on each capture input
FIGURE 17-2:
2010 Microchip Technology Inc.
(16-bits/channel) on the CAP1, CAP2 and CAP3
pins
Measurement Operating modes for each channel
channel
Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active.
CAP1 Pin
velcap
Input Capture
2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.
(2)
FLTCK<2:0>
VELM
1
0
MUX
Noise
Filter
3
INPUT CAPTURE BLOCK DIAGRAM FOR IC1
Prescaler
1, 4, 16
CAP1M<3:0> Q Clocks
Q Clocks
4
Interrupt
Decode
Select
Mode
Reset/
Clock/
Logic
and
CAP1M<3:0>
PIC18F2331/2431/4331/4431
First Event
Reset
CAP1BUF_clk
Input Channel 1 (IC1) includes a Special Event
Figure
measurement logic. A representative block diagram is
shown in
is Timer5.
Trigger that can be configured for use in Velocity
Measurement mode. Its block diagram is shown in
Special Event Trigger features or additional velocity
Event Trigger
Special
IC1_TR
Reset
IC1IF
17-2. IC2 and IC3 are similar, but lack the
Figure
17-3. Please note that the time base
Timer5 Logic
CAP1BUF/VELR
TMR5
Control
Timer
Reset
DS39616D-page 153
(1)
Reset
Control
Timer5 Reset
Clock
Reset
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