PIC18F24J10T-I/SS Microchip Technology, PIC18F24J10T-I/SS Datasheet - Page 2
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PIC18F24J10T-I/SS
Manufacturer Part Number
PIC18F24J10T-I/SS
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
Specifications of PIC18F24J10T-I/SS
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F24J10T-I/SSTR
PIC18F45J10 FAMILY
TABLE 2:
DS80494B-page 2
Timer1
EUSART
EUSART
EUSART
EUSART
MSSP
MSSP
Core
EUSART
ECCP
MSSP
EUSART
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
16-Bit
Counter
Reception
Baud Rate
Buffer
9-Bit
SPI
I
Program
Memory
Transmission
PWM
I
Interrupt
2
2
C™
C™
SILICON ISSUE SUMMARY
Feature
Number
Item
10.
11.
12.
1.
2.
3.
4.
5.
6.
7.
8.
9.
In 16-Bit Asynchronous Counter mode or 16-Bit
Asynchronous Oscillator mode, the TMR1H buffer
does not update when TMR1L is read.
In asynchronous duplex communication, received
data can get corrupted if any bit of the TXSTA register
is modified during reception.
In Synchronous mode, EUSART baud rates using
SPBRG values of '0' and '1' may not function
correctly.
After the last received byte has been read from the
EUSART Receive Buffer (RCREG), the value is no
longer valid for subsequent read operations.
In 9-Bit Asynchronous Full-Duplex Receive mode,
received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after RCIDL
(BAUDCON<6>) is set.
In SPI mode, the Buffer Full flag bit (BF,
SSPxSTAT<0>), the Write Collision Detect bit
(WCOL, SSPxCON1<7>) and the Receive Overflow
Indicator bit (SSPOV, SSPxCON1<6>) are not reset
upon disabling the SPI module.
After a Power-on Reset, I
properly if only the SCLx and SDAx pins have been
configured as either inputs or outputs.
Writes to program memory address, 300000h, that
are not blocked, can cause different locations of the
program memory to become corrupted.
In rare situations, one or more extra zero bytes may
appear in packets transmitted with the module in
Asynchronous mode.
When switching direction in Full-Bridge PWM mode,
the modulated outputs will switch immediately instead
of waiting for the next PWM cycle. This may generate
unexpected short pulses on the modulated outputs.
When configured for I
module may not receive the correct data, in extremely
rare cases. This occurs only if the Serial Receive/
Transmit Buffer Register (SSPBUF) is not read within
a window after the SSPxIF interrupt (PIR1<3>) has
occurred.
In rare situations, unexpected results may occur if
interrupts are disabled and enabled and a two-cycle
instruction is executed.
Issue Summary
2
C slave reception, the MSSP
2
C mode may not initialize
2009 Microchip Technology Inc.
Affected Revisions
A2
X
X
X
X
X
X
X
X
X
X
X
X
A3
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
X
X
X
X
(1)