PIC18F4420T-I/PT Microchip Technology, PIC18F4420T-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F4420T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4420T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 18-3:
4. Module: 10-Bit Analog-to-Digital
5. Module: MSSP
 2009 Microchip Technology Inc.
bit 1
bit 0
When the AD clock source is selected as 2 T
RC (when ADCS<2:0> = 000 or x11), in extremely
rare cases, the E
E
data sheet specification at codes 511 and 512 only.
Work around
Select the AD clock source as 4 T
16 T
2 T
Date Codes that pertain to this issue:
All engineering and production devices.
With MSSP in SPI Master mode, F
Timer2/2 clock rate, and CKE = 0, a write collision
may occur if SSPBUF is loaded immediately after
the transfer is complete. A delay may be required
after the MSSP Interrupt Flag bit, SSPIF, is set or
the Buffer Full bit, BF, is set and before writing
SSPBUF. If the delay is insufficiently short, a write
collision may occur as indicated by the WCOL bit
being set.
Work around
Add a software delay of one SCK period after
detecting the completed transfer and prior to
updating the SSPBUF contents. Verify the WCOL
bit is clear after writing SSPBUF. If the WCOL is
set, clear the bit in software and rewrite the
SSPBUF register.
Date Codes that pertain to this issue:
All engineering and production devices.
DL
OSC
OSC
(Differential Linearity Error) may exceed the
or RC.
, 32 T
Converter
WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin with the interrupt generated on the falling edge; bit
0 = RX pin is not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
OSC
cleared in hardware on following rising edge
cleared in hardware upon completion.
BAUDCON: BAUD RATE CONTROL REGISTER (CONTINUED)
IL
or 64 T
(Integral Linearity Error) and
OSC
and avoid selecting
OSC
OSC
, 8 T
PIC18F2420/2520/4420/4520
/64 or
OSC
OSC
or
,
6. Module: Enhanced Capture/Compare/
With the ECCP configured for Half-Bridge PWM
mode (CCP1M<3:0> = 1110), the output may be
corrupted for particular duty cycle selections.
Affected duty cycle values are 0 though 3, and
every subsequent increment of 4 (i.e., 7, 11, 15,
19, etc.).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
PWM (ECCP)
DS80363C-page 3