PIC18F452-E/ML Microchip Technology, PIC18F452-E/ML Datasheet - Page 3

• Manufacturer Part Number: PIC18F452-E/ML
• Description: 44 PIN, 32KB ENH FLASH, 1536 RAM, 34 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F452-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. Module: Core (Program Memory Space)
© 2005 Microchip Technology Inc.
Note:
Under certain conditions, the execution of some
control operations may yield unexpected results.
This has been observed when any of the following
instructions vector code execution across the
4000h program memory address boundary:
• CALL
• GOTO
• RETURN
• RETLW
• RETFIE
In addition, unexpected operation may result when
an interrupt causes the device to jump across the
4000h boundary to the appropriate interrupt
vector.
There are no known issues related to any of these
instructions when execution occurs strictly above
or below the 4000h address boundary.
Work around
Three possible solutions are presented. Others
may exist. It is recommended to implement any
one, or any combination of the three, as needed.
1. Insert a data word of value FFFFh as the first
2. Insert a data word of FFFFh at the interrupt
3. Insert a data word of value FFFFh immediately
In each of these instances, the literal data behaves
as a NOP instruction when executed. Using the
actual NOP instruction instead of a literal FFFFh
may not have the same results.
Date Codes that pertain to this issue:
All engineering samples and devices with date
codes up to and including 0252 (Year 2002, Work
Week 52).
instruction in the destination of a CALL or
GOTO.
vector address(es) (0008h and/or 0018h).
following any RETURN, RETLW, or RETFIE
instruction.
This issue applies only to PIC18F252
and PIC18F452 devices with 32K words of
Flash program memory. PIC18F242 and
PIC18F442 devices are not affected.
7. Module: Data EEPROM
8. Module: MSSP (All I
When reading the data EEPROM, the contents of
the EEDATA register may be corrupted if the RD
bit (EECON1<0>) is set immediately following a
write to the address byte (EEADR). The actual
contents of the data EEPROM remain unaffected.
Work around
Do not set EEADR immediately before the
execution of a read. Write to EEADR at least one
instruction cycle before setting the RD bit. The
instruction between the write to EEADR and the
read can be any valid instruction including a NOP.
Date Codes that pertain to this issue:
All engineering and production devices.
The Buffer Full (BF) flag bit of the SSPSTAT regis-
ter (SSPSTAT<0>) may be inadvertently cleared
even when the SSPBUF register has not been
read. This will occur only when the following two
conditions occur simultaneously:
• The four Least Significant bits of the BSR register
• Any instruction that contains C9h in its 8 Least
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh.
In addition to those proposed below, other
solutions may exist.
1. When developing or modifying code, keep
2. If accessing a part of Bank 15 is required and
3. If pointing the BSR to Bank 15 is unavoidable,
Date Codes that pertain to this issue:
All engineering and production devices.
are equal to 0Fh (BSR<3:0> = 1111) and
Significant bits (i.e., register file addresses,
literal data, address offsets, etc.) is executed.
these guidelines in mind:
• Assign 12-bit addresses to all variables.
• Do not set the BSR to point to Bank 15
• Allow the assembler to manipulate the
the use of Access Banking is not possible,
consider using indirect addressing.
review the absolute file listing. Verify that no
instructions contain C9h in the 8 Least Significant
bits while the BSR points to Bank 15 (BSR = 0Fh).
This allows the assembler to know when
Access Banking can be used.
(BSR = 0Fh).
access bit present in most instructions.
Accessing the SFRs in Bank 15 will be done
through the Access Bank. Continue to use
the BSR to select all GPR Banks.
Modes)
PIC18FXX2
2
C™ and SPI™
DS80127G-page 3