PIC18F4550T-I/PT Microchip Technology, PIC18F4550T-I/PT Datasheet - Page 2

• Manufacturer Part Number: PIC18F4550T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4550T-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: GPIODM-KPLCD - BOARD DEMO LCD GPIO EXP KEYPADI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD
• Lead Free Status / Rohs Status: Details

PIC18F2455/2550/4455/4550
2. Module: Timer1 Module
12.7
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed fol-
lowing a later Timer1 increment. This can be done by
monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L reg-
ister pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator; in this case, one-half
period of the clock is 15.25 μs.
The Real-Time Clock application code in Example 12-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
(Example 12-1 appears on page 1 of this errata.)
3. Module: Universal Serial Bus (USB)
DS80278A-page 2
The following text, Section 12.7 “Considerations
in Asynchronous Counter Mode”, is new. It
defines the proper method to update the TMR1
registers in Asynchronous mode.
Section 12.7 is located after Section 12.6 “Using
Timer1 as a Real-Time Clock” in the data sheet.
In Subsection 17.2.2.8 “Internal Regulator,” the
following corrections should be noted (changes
and added text appear in bold for the purposes of
this errata):
• In the second paragraph, the first sentence is
• In the final note box of the section, Note 2 is
corrected to read, “The regulator is disabled by
default and can be enabled through the
VREGEN Configuration bit.”
The sentence originally stated, “The regulator is
enabled by default and can be disabled through
the VREGEN Configuration bit.”
corrected to read, “V
equal to V
regulator disabled.”
The sentence originally stated, “V
greater than V
regulator disabled.”
Considerations in Asynchronous
Counter Mode
USB
USB
at all times, even with the
at all times, even with the
DD
must be greater than or
DD
must be
4. Module: Master Synchronous Serial Port
5. Module: 10-Bit Analog-to-Digital (A/D)
6. Module: Special Features of the CPU
In Section 19.3.5 “Master Mode,” the second
paragraph of the second column is corrected to
read, “This allows a maximum data rate (at
48 MHz) of 12.00 Mbps.”
The sentence originally stated, “This allows a
maximum data rate (at 48 MHz) of 2.00 Mbps.”
In Register 21-1: “ADCON0: A/D Control
Register 0,” the display and the detailed bit
description for bit 5 is corrected to “VCFG1”,
rather than “VCFG0”. All other bit 5 display and
descriptions are correct in the device data sheet.
In Section 25.9.1 “Dedicated ICD/ICSP Port”,
the second sentence of the fourth paragraph is
corrected to state, “When V
MCLR/V
pin is ignored”. This refers to the high-voltage
programming voltage level for ICSP™ (DC
Specification D110).
The sentence originally stated, “When V
on the MCLR/V
ICRST/ICV
referred to the maximum input voltage tolerated by
the pin as an I/O (DC specification D040).
PP
(MSSP) Module
Converter Module
/RE3 pin, the state of the ICRST/ICV
PP
pin is ignored”. That incorrectly
PP
© 2006 Microchip Technology Inc.
/RE3 pin, the state of the
IHH
is seen on the
IH
is seen
PP