PIC18F64J90-I/PT Microchip Technology, PIC18F64J90-I/PT Datasheet
PIC18F64J90-I/PT
Specifications of PIC18F64J90-I/PT
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PIC18F64J90-I/PT Summary of contents
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... PIC18F65J90 • PIC18F86J11 • PIC18F65J50 • PIC18F86J10 • PIC18F65J15 • PIC18F85J90 • PIC18F65J11 • PIC18F85J50 • PIC18F65J10 • PIC18F85J15 • PIC18F64J90 • PIC18F85J11 • PIC18F64J11 • PIC18F85J10 • PIC18F63J90 • PIC18F84J90 • PIC18F63J11 • PIC18F84J11 • PIC18F83J90 • PIC18F83J11 2009 Microchip Technology Inc. ...
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... Pin Description P Programming Enable P Power Supply P Ground P Internal Voltage Regulator Enable P Regulated Power Supply for Microcontroller Core I Filter Capacitor for On-Chip Voltage Regulator I Serial Clock I/O Serial Data P Internal USB 3.3V Voltage Regulator ) and ground ( during programming. DD 2009 Microchip Technology Inc. ...
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... FIGURE 2-1: PIC18F6XJXX PIN DIAGRAMS 64-Pin TQFP The following devices are included in 64-pin TQFP parts: • PIC18F67J93 • PIC18F67J90 • PIC18F66J93 • PIC18F66J90 • PIC18F65J90 • PIC18F64J90 • PIC18F63J90 RE1 1 RE0 2 RG0 3 RG1 4 RG2 5 RG3 6 MCLR 7 RG4 DDCORE CAP RF7 11 RF6 ...
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... PIC18F85J50 • PIC18F84J11 • PIC18F86J16 • PIC18F83J11 • PIC18F86F15 • PIC18F87J10 • PIC18F85J15 • PIC18F86J10 • PIC18F85J10 PIC18F8XJXX RJ2 60 RJ3 59 RB0 58 RB1 57 RB2 56 RB3 55 RB4 54 RB5 53 RB6/KBI2/PGC OSC2 50 OSC1 RB7/KBI3/PGD 47 RC5 46 RC4 45 RC3 44 RC2 43 RJ7 42 RJ6 41 2009 Microchip Technology Inc. ...
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... SEG24/AN11/C1INA/RF6 14 SEG23/AN10/C1INB/C /RF5 VREF 15 SEG22/AN9/C2INA/RF4 16 SEG21/AN8/C2INB/RF3 17 SEG20/AN7/C1OUT/RF2 18 CH1- 19 CH1 Note 1: The CCP2 pin placement depends on the setting of the CCP2MX configuration bit. Note: Pinouts are subject to change. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX • PIC18F86J72 PIC18F8XJ72 SDOA 60 SCKA 59 CSA 58 SEG30/INT0/RB0 57 SEG8/RTCC/INT1/RB1 56 SEG9/CTED1/INT2/RB2 ...
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... Note 1: These are typical operating voltages. Refer to Section 6.0 “AC/DC Characteristics and Timing Requirements for Program/Verify Test Mode”. CONNECTIONS FOR THE ON-CHIP REGULATOR ): DD (1) 3.3V PIC18F6XJXX/8XJXX V DD ENVREG V /V DDCORE CAP (1) 3.3V PIC18F6XJXX/8XJXX V DD ENVREG V /V DDCORE CAP V SS 2009 Microchip Technology Inc. ...
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... The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write operations. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX TABLE 2-2: Device PIC18F63J11 PIC18F63J90 PIC18F83J11 PIC18F83J90 PIC18F64J11 PIC18F64J90 PIC18F84J11 PIC18F84J90 PIC18F65J10 PIC18F65J11 PIC18F65J50 PIC18F65J90 PIC18F85J10 PIC18F85J11 PIC18F85J50 PIC18F85J90 PIC18F65J15 ...
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... Configuration Configuration Space Space Configuration Configuration Configuration Words Words Configuration Configuration Configuration Space Space Device IDs Device IDs Device IDs (1) 000000h 007FFFh 00BFFFh 00FFFFh 017FFFh 01FFFFh 1FFFFFh 200000h Space 2FFFFFh 300000h Words (2) 300007h Space 3FFFFEh 3FFFFFh 2009 Microchip Technology Inc. ...
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... Note 1: Sizes of memory areas are not to scale. Sizes of accessible memory areas are enhanced to show detail. 2: Configuration Words at 300006h and 300007h are not implemented on PIC18FXXJ11/XXJ90/XXJ93/XXJ72 devices. 3: PIC18F66J11/67J11/86J11/87J11 memory map is not included in this PIC18FXXJ11/XXJ90/XXJ72 memory map (see Figure 2-7). 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX PIC18FX5J11/X5J90 PIC18FX6J9X/X6J72 ...
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... Configuration Configuration Space Space Configuration Configuration Configuration Words Words Configuration Configuration Configuration Space Space Device IDs Device IDs Device IDs (1) X7J11 000000h 007FFFh 00FFFFh 017FFFh 01FFFFh 1FFFFFh 200000h Space 2FFFFFh 300000h Words (2) 300007h Space 3FFFFEh 3FFFFFh 2009 Microchip Technology Inc. ...
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... Memory spaces are read-only (Device IDs) or cannot be directly programmed by ICSP™ (Configuration Words). Note 1: Sizes of memory areas are not to scale. Sizes of accessible memory areas are enhanced to show detail. 2: Configuration Words at 300006h and 300007h are not implemented on PIC18F6XJ50/8XJ5X devices. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX PIC18FX6J16 PIC18FX7J11 000000h ...
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... PGC and PGD before removing V When V is reapplied to MCLR, the device will enter IH the ordinary operational mode and begin executing the application instructions Program/Verify Entry Code = 4D434850h ... b31 b30 b29 b28 b27 b3 P2B P2A , removed, an interval must P20 P12 2009 Microchip Technology Inc. ...
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... Command 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX Throughout this specification, commands and data are presented as illustrated in Table 2-4. The 4-bit command is shown, Most Significant bit (MSb) first. The command operand, or “Data Payload”, is shown <MSB><LSB>. Figure 2-12 demonstrates how to serially present a 20-bit command/operand to the device ...
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... Write 80h TO 3C0004h to erase entire device. NOP 00 00 Hold PGD low until erase 00 00 completes. BULK ERASE FLOW Start Write 0101h to 3C0005h Write 8080h to 3C0004h to Erase Entire Device Delay P11 Time Done P11 Erase Time 16-Bit Data Payload 2009 Microchip Technology Inc. ...
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... Step 3: Enable erase and erase single row. 0000 88 A6 0000 82 A6 0000 00 00 Step 4: Repeat step 3, with Address Pointer incremented by 1024 until all rows are erased. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX FIGURE 3-3: Addr = Addr + 1024 Erase a Core Instruction BSF ...
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... Core Instruction BSF EECON1, WREN MOVLW <Addr[21:16]> MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9. 2009 Microchip Technology Inc. ...
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... FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING ( PGC P5 PGD 4-Bit Command 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No Bytes Written? Yes Start Write Sequence and Hold PGC High Until Done ...
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... MOVLW <Addr[8:15]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Repeat as many times as necessary to fill the write buffer. Write 2 bytes and start programming. NOP - hold PGC high for time P9. BCF EECON1, WREN 2009 Microchip Technology Inc. ...
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... PGD PGD = Input 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read ...
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... Given that Blank Checking is merely code verification with FFh expect data, refer to Section 4.2 “Verify Code Memory and Configuration Word” for implementation details. FIGURE 4-3: Start Blank Check Device Device Blank? Abort Failure, Report Error BLANK CHECK FLOW Is Yes Continue No 2009 Microchip Technology Inc. ...
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... Words are unimplemented, they will not change the device’s configuration. The Configuration and Device ID registers are summarized in Table 5-2. A listing of the individual Configuration bits and their options is provided in Table 5-3. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX TABLE 5-1: Configuration Byte CONFIG1L ...
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... FOSC1 FOSC0 11-- -111 FOSC1 FOSC0 11-1 1111 WDTPS1 WDTPS0 ---- 1111 — — ---- ---- RTCOSC — ---- --1- (4,7,8) ECCPMX CCP2MX ---- --11 (7) (4,7,8) (7) ECCPMX CCP2MX ---- 1111 (4,7,8) (6) ECCPMX CCP2MX ---- 1-11 REV1 REV0 See Table 5-4 DEV4 DEV3 See Table 5-4 2009 Microchip Technology Inc. ...
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... T13CKI input is not available as secondary clock source without enabling Note 1: Implemented in PIC18FXXJ5X devices only. 2: Implemented in PIC18F66J11/66J16/67J11/86J11/86J16/87J11 devices only. 3: Implemented in 80-pin devices only. 4: Implemented in PIC18FX6J9X and PIC18FX7J9X. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX Description purpose I/O pins (Legacy mode) of FOSC<1:0>; INTRC selected when OSCCON<1:0> OSCCON<1:0> T1OSCEN DS39644L-page 23 ...
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... DS39644L-page 24 Description (1) on RA7, ECPLL oscillator used by USB EC oscillator used by USB RA6 and port function on RA7 RA6, port function on RA7 RA6 and RA7 (2) on RA7 and RA7 RA6, port function on RA7 RA6 and RA7 (4) (INTOSCPLLO) (INTOSCPLL) 2009 Microchip Technology Inc. ...
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... Implemented in PIC18F66J11/66J16/67J11/86J11/86J16/87J11 devices only. 3: Implemented in 80-pin devices only. 4: Implemented in PIC18FX6J9X and PIC18FX7J9X. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX Description ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 or with RB3 in Extended Microcontroller mode (80-pin devices only) ...
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... Device ID PIC18F6XJXX/8XJXX devices is Table 5-4. TABLE 5-4: DEVICE ID VALUE Device PIC18F63J11 PIC18F63J90 PIC18F64J11 PIC18F64J90 PIC18F65J10 PIC18F65J11 PIC18F65J15 PIC18F65J50 PIC18F65J90 PIC18F66J10 PIC18F66J11 PIC18F66J15 PIC18F66J16 PIC18F66J50 PIC18F66J55 PIC18F66J90 PIC18F66J93 Legend: The ‘x’s in DEVID1 are reserved for the device revision code. ...
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... PIC18F86J55 PIC18F86J72 PIC18F86J90 PIC18F86J93 PIC18F87J10 PIC18F87J11 PIC18F87J50 PIC18F87J72 PIC18F87J90 PIC18F87J93 Legend: The ‘x’s in DEVID1 are reserved for the device revision code. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX Device ID Value DEVID2 15h 101x xxxx 44h 100x xxxx 41h 100x xxxx 50h ...
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... Disabled CFGB60 + SUM(0000:3FF7h) Enabled Disabled CFGB60 + SUM(0000:5FF7h) Enabled Disabled CFGB60 + SUM(0000:7FF7h) Enabled Disabled CFGB80 + SUM(0000:1FF7h) Enabled Disabled CFGB80 + SUM(0000:3FF7h) Enabled Disabled CFGB80 + SUM(0000:5FF7h) Enabled Disabled CFGB80 + SUM(0000:7FF7h) Enabled 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2009 Microchip Technology Inc. ...
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... TABLE 5-5: CHECKSUM EQUATION FOR PIC18F6XJXX/8XJXX (CONTINUED) Family Device PIC18F63J90 PIC18F64J90 PIC18F64J95 PIC18F65J90 PIC18F85J90 PIC18F83J90 PIC18F84J90 PIC18F84J95 PIC18F85J90 CFGB = Byte sum of [(CW1 & 0CE1h) + (CW2 & 0FC7h) + (CW3 & 0100h)] PIC18F65J10 PIC18F65J15 PIC18F66J10 PIC18F66J15 PIC18F67J10 PIC18F87J10 PIC18F85J10 PIC18F85J15 PIC18F86J10 PIC18F86J15 PIC18F87J10 CFGB80 = Byte sum of [(CW1 & ...
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... Disabled CFGB60 + SUM(0000:FFF7h) Enabled Disabled CFGB60 + SUM(00000:17FF7h) Enabled Disabled CFGB60 + SUM(00000:1FFF7h) Enabled Disabled CFGB80 + SUM(0000:BFF7h) Enabled Disabled CFGB80 + SUM(0000:FFF7h) Enabled Disabled CFGB80 + SUM(00000:17FF7h) Enabled Disabled CFGB80 + SUM(00000:1FFF7h) Enabled 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2009 Microchip Technology Inc. ...
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... Configuration Word CFGB = Configuration Block (Masked) Note: CW3 address is the last location – implemented program memory; CW2 is the last location – 4; CW1 is the last location – 6. 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX Read Code Protection Checksum Computation Disabled CFGB60 + SUM(0000:7FF7h) Enabled ...
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... Normal programming (Note 2) meet AC specifications F Required for controller core operation when voltage regulator is enabled For PIC18F87J10, PIC18F85J90 and PIC18F85J11 family parts For PIC18F87J50, ms PIC18F87J11, PIC18F87J90, PIC18F87J93 and PIC18F87J72 family parts ms ms and V , respectively. SS 2009 Microchip Technology Inc. ...
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... PGD to Second MCLR Note 1: V must be supplied to the V DDCORE Section 2.1.1 “On-Chip Voltage Regulator” for more information must also be supplied to the AV DD regulator is used. AV and AV DD 2009 Microchip Technology Inc. PIC18F6XJXX/8XJXX Min Max 400 — 100 — 10 — 20 — 1 — ...
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... PIC18F6XJXX/8XJXX NOTES: DS39644L-page 34 2009 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...