PIC18F67J60T-I/PT Microchip Technology, PIC18F67J60T-I/PT Datasheet - Page 117
![128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60T-I/PT
Manufacturer Part Number
PIC18F67J60T-I/PT
Description
128KB Flash, 12KB RAM, 10BASE-T Ethernet 64 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F67J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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7.7
In 8-Bit Data Width mode, the external memory bus
operates only in Multiplexed mode; that is, data shares
the eight Least Significant bits of the address bus.
Figure 7-6 shows an example of 8-Bit Multiplexed mode
for 100-pin devices. This mode is used for a single 8-bit
memory connected for 16-bit operation. The instructions
will be fetched as two 8-bit bytes on a shared
data/address bus. The two bytes are sequentially
fetched within one instruction cycle (T
designer must choose external memory devices accord-
ing to timing calculations based on 1/2 T
instruction rate). For proper memory speed selection,
glue logic propagation delay times must be considered,
along with setup and hold times.
The Address Latch Enable (ALE) pin indicates that the
address bits, AD<15:0>, are available on the external
memory interface bus. The Output Enable signal (OE)
FIGURE 7-6:
© 2009 Microchip Technology Inc.
8-Bit Data Width Mode
Note 1:
2:
PIC18F97J60
Upper order address bits are used only for 20-bit address width. The upper AD byte is used for all
address widths except 8-bit.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
AD<15:8>
A<19:16>
8-BIT MULTIPLEXED MODE EXAMPLE
AD<7:0>
WRL
ALE
BA0
OE
CE
(1)
(1)
CY
). Therefore, the
CY
(2 times the
373
PIC18F97J60 FAMILY
will enable one byte of program memory for a portion of
the instruction cycle, then BA0 will change and the
second byte will be enabled to form the 16-bit instruc-
tion word. The Least Significant bit of the address, BA0,
must be connected to the memory devices in this
mode. The Chip Enable signal (CE) is active at any
time that the microcontroller accesses external
memory, whether reading or writing. It is inactive
(asserted high) whenever the device is in Sleep mode.
This process generally includes basic EPROM and
Flash devices. It allows table writes to byte-wide
external memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate level of the BA0
control line is strobed on the LSb of the TBLPTR.
D<7:0>
A<19:0>
D<15:8>
Address Bus
Data Bus
Control Lines
A<x:1>
A0
D<7:0>
CE
OE
WR
DS39762E-page 117
(2)
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