PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 2
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PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F1230/1330
4. Module: Comparator Voltage Reference
TABLE 1:
DS80308D-page 2
CVRCON<7>
CVREN
The
(CV
CV
The CV
the following inputs to the comparators:
• Scaled V
• Scaled V
• No reference (disabled)
Table 1 shows how the CVREN and CVRSS bits
are configured to enable the options.
0
1
1
REF
REF
comparator
module.
) does not offer the option of bypassing the
REF
REF
DD
CVRCON<4>
VOLTAGE REFERENCE
OUTPUT
x (don’t care) Disabled
module offers the option of providing
CVRSS
0
1
voltage
CV
CV
REF
REF
reference
Comparator
Reference
uses AV
uses V
REF
module
DD
5. Module: Enhanced Universal
1.
2.
3.
4.
5.
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTA <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 T
Disable
PIE1<5> = 0).
Disable the EUSART (RCSTA <7> = 0).
Re-enable the EUSART (RCSTA <7> = 1).
Re-enable receive interrupts (PIE1<5> = 1).
(This is the first T
Execute a NOP instruction.
(This is the second T
Date Codes that pertain to this issue:
All engineering and production devices.
RCSTA <7> = 0)
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
Receive
delay after re-enabling the EUSART.
CY
© 2008 Microchip Technology Inc.
delay.)
CY
Interrupts
delay.)
(RCIE
bit,