PIC18LF2423-I/ML Microchip Technology, PIC18LF2423-I/ML Datasheet - Page 26
![16KB, Flash, 768bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2423-I/ML
Manufacturer Part Number
PIC18LF2423-I/ML
Description
16KB, Flash, 768bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
Specifications of PIC18LF2423-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIC18F2XXX/4XXX FAMILY
4.3
A configuration address may be read and output on
PGD via the 4-bit command, ‘1001’. Configuration data
is read and written in a byte-wise fashion, so it is not
necessary to merge two bytes into a word prior to a
compare. The result may then be immediately
compared to the appropriate configuration data in the
programmer’s memory for verification. Refer to
Section 4.1 “Read Code Memory, ID Locations and
Configuration Bits”
reading configuration data.
4.4
Data EEPROM is accessed, one byte at a time, via an
Address Pointer (register pair: EEADRH:EEADR) and
a data latch (EEDATA). Data EEPROM is read by load-
ing EEADRH:EEADR with the desired memory location
and initiating a memory read by appropriately configur-
ing the EECON1 register. The data will be loaded into
EEDATA, where it may be serially output on PGD via
the 4-bit command, ‘0010’ (Shift Out Data Holding
register). A delay of P6 must be introduced after the
falling edge of the 8th PGC of the operand to allow
PGD to transition from an input to an output. During this
time, PGC must be held low (see
The command sequence to read a single byte of data
is shown in
TABLE 4-2:
DS39622L-page 26
Step 1: Direct access to data EEPROM.
Step 2: Set the data EEPROM Address Pointer.
Step 3: Initiate a memory read.
Step 4: Load data into the Serial Data Holding register.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0010
4-Bit
Verify Configuration Bits
Read Data EEPROM Memory
The <LSB> is undefined. The <MSB> is the data.
Table
9E A6
9C A6
0E <Addr>
6E A9
OE <AddrH>
6E AA
80 A6
50 A8
6E F5
00 00
<MSB><LSB>
4-2.
READ DATA EEPROM MEMORY
Data Payload
for implementation details of
Figure
4-4).
BCF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
MOVF
MOVWF
NOP
Shift Out Data
EECON1, EEPGD
EECON1, CFGS
<Addr>
EEADR
<AddrH>
EEADRH
EECON1, RD
EEDATA, W, 0
TABLAT
(1)
FIGURE 4-3:
Core Instruction
No
Move to TABLAT
Shift Out Data
READ DATA EEPROM
FLOW
2010 Microchip Technology Inc.
Address
Done?
Read
Done
Start
Byte
Set
Yes