PIC18LF25J10-I/ML Microchip Technology, PIC18LF25J10-I/ML Datasheet - Page 101

• Manufacturer Part Number: PIC18LF25J10-I/ML
• Description: Microcontroller
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF25J10-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPIC, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180012 - MODULE PLUG-IN 18LF25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 10-3:
© 2009 Microchip Technology Inc.
RA0/AN0
RA1/AN1
RA2/AN2/
V
RA3/AN3/V
RA5/AN4/SS1/
C2OUT
OSC2/CLKO
OSC1/CLKI
Legend:
REF
-/CV
Pin
REF
REF
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
+
PORTA I/O SUMMARY
Function
C2OUT
CV
V
OSC2
CLKO
OSC1
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA5
AN4
SS1
REF
REF
REF
+
-
Setting
TRIS
0
1
1
0
1
1
0
1
1
1
x
0
1
1
1
0
1
1
1
0
x
x
x
x
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
TTL
DIG
DIG
I/O
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D Input Channel 0 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
A/D Input Channel 1 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
A/D Input Channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
A/D and comparator voltage reference low input.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D Input Channel 3 and Comparator C1+ input. Default input
configuration on POR.
A/D and comparator voltage reference high input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D Input Channel 4. Default configuration on POR.
Slave select input for MSSP1 (MSSP1 module).
Comparator 2 output; takes priority over port data.
Main oscillator feedback output connection (HS mode).
System cycle clock output (F
Main oscillator input connection.
Main clock input connection.
REF
output enabled.
PIC18F45J10 FAMILY
REF
output enabled.
OSC
Description
/4) in RC and EC Oscillator modes.
DS39682E-page 99