PIC18LF4580-I/ML Microchip Technology, PIC18LF4580-I/ML Datasheet - Page 164

• Manufacturer Part Number: PIC18LF4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
15.1
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 15-1:
FIGURE 15-2:
DS39637D-page 164
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Timer3 Operation
T1OSI
T1OSI
CCP/ECCP Special Event Trigger
CCP/ECCP Special Event Trigger
Timer1 Oscillator
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
TIMER3 BLOCK DIAGRAM
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
(1)
(1)
T3ECCP1
T3ECCP1
TMR3CS
TMR3CS
Internal
Clock
F
Clock
Internal
F
OSC
OSC
/4
/4
1
0
1
0
Clear TMR3
Timer1 clock input
Clear TMR3
Prescaler
1, 2, 4, 8
Prescaler
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator if enabled.
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
1, 2, 4, 8
2
2
TMR3L
TMR3L
8
Sleep Input
Synchronize
Sleep Input
8
Synchronize
Detect
Detect
High Byte
High Byte
TMR3H
TMR3
TMR3
8
© 2009 Microchip Technology Inc.
8
8
Internal Data Bus
1
0
1
0
Read TMR1L
Write TMR1L
on Overflow
on Overflow
TMR3IF
TMR3IF
Set
Set
Timer3
On/Off
Timer3
On/Off