PIC24FJ64GA006T-I/PT Microchip Technology, PIC24FJ64GA006T-I/PT Datasheet - Page 30
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PIC24FJ64GA006T-I/PT
Manufacturer Part Number
PIC24FJ64GA006T-I/PT
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ64GA006-IPT.pdf
(240 pages)
3.PIC24FJ64GA006-IPT.pdf
(22 pages)
Specifications of PIC24FJ64GA006T-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DV164033, MA240013, AC164127, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA006T-I/PT
Manufacturer:
MICROCHIP
Quantity:
1 000
Company:
Part Number:
PIC24FJ64GA006T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC24FJXXXGA0XX
4.5.2
After code memory is programmed, the contents of
memory can be verified to ensure that programming
was successful. Verification requires code memory to
be read back and compared against the copy held in
the programmer’s buffer.
The READP command can be used to read back all of
the programmed code memory.
Alternatively, you can have the programmer perform
the verification after the entire device is programmed
using a checksum computation.
TABLE 4-2:
DS39768D-page 30
I2C1SEL
DEBUG
FCKSM1:FCKSM0
FNOSC2:FNOSC0
FWDTEN
GCP
GWRP
ICS
Note 1:
Bit Field
2:
(1)
Available on 28 and 44-pin packages only.
Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher.
PROGRAMMING VERIFICATION
PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION
CW2<10:8>
CW2<7:6>
CW1<13>
CW1<12>
CW1<11>
Register
CW2<2>
CW1<7>
CW1<8>
I2C1 Pin Mapping bit
1 = Default location for SCL1/SDA1 pins
0 = Alternate location for SCL1/SDA1 pins
Background Debug Enable bit
1 = Device will reset in User mode
0 = Device will reset in Debug mode
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRCDIV) oscillator with postscaler
110 = Reserved
101 = Low-Power RC (LPRC) oscillator
100 = Secondary (SOSC) oscillator
011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
000 = Fast RC (FRC) oscillator
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
ICD Communication Channel Select bit
1 = Communicate on PGC2/EMUC2 and PGD2/EMUD2
0 = Communicate on PGC1/EMUC1 and PGD1/EMUD1
clearing the SWDTEN bit in the RCON register will have no effect)
disabled by clearing the SWDTEN bit in the RCON register)
4.6
4.6.1
The PIC24FJXXXGA0XX family has Configuration bits
stored in the last two locations of implemented program
memory (see Table 2-2 for locations). These bits can
be set or cleared to select various device configura-
tions. There are three types of Configuration bits:
system operation bits, code-protect bits and unit ID bits.
The system operation bits determine the power-on
settings for system level components, such as
oscillator and Watchdog Timer. The code-protect bits
prevent program memory from being read and written.
The register descriptions for the CW1 and CW2
Configuration registers are shown in Table 4-2.
Configuration Bits Programming
Description
OVERVIEW
© 2008 Microchip Technology Inc.