S29AL008D70TFI010 Spansion Inc., S29AL008D70TFI010 Datasheet - Page 30

• Manufacturer Part Number: S29AL008D70TFI010
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of S29AL008D70TFI010

• Memory Size: 8Mbit
• Memory Configuration: 1M X 8 / 512K X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

30
Reading Toggle Bits DQ6/DQ2
DQ5: Exceeded Timing Limits
DQ3: Sector Erase Timer
for erasure. Thus, both status bits are required for sector and mode information.
Refer to
Figure 6, on page 31
section “DQ2: Toggle Bit II” explains the algorithm. See also the
I, on page 29
gram.
graphical form.
Refer to
initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in
a row to determine whether a toggle bit is toggling. Typically, the system would
note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If
the toggle bit is not toggling, the device completed the program or erase opera-
tion. The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer toggling, the device success-
fully completed the program or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit
is toggling and DQ5 has not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algo-
rithm when it returns to determine the status of the operation (top of
on page
DQ5 indicates whether the program or erase time exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a 1. This is a failure con-
dition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a lo-
cation that is previously programmed to 0. Only an erase operation can
change a 0 back to a 1. Under this condition, the device halts the operation,
and when the operation exceeds the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the reset command to return
the device to reading array data.
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not an erase operation started. (The sector erase timer does
not apply to the chip erase command.) If additional sectors are selected for era-
sure, the entire time-out also applies after each additional sector erase
command. When the time-out is complete, DQ3 switches from 0 to 1. The system
may ignore DQ3 if the system can guarantee that the time between additional
Figure 21, on page 46
Figure 6, on page 31
Table 6, on page 32
31).
subsection.
shows the toggle bit algorithm in flowchart form, and the
Figure 20, on page 45
to compare outputs for DQ2 and DQ6.
D a t a
for the following discussion. Whenever the system
shows the differences between DQ2 and DQ6 in
S29AL008D
S h e e t
shows the toggle bit timing dia-
DQ6: Toggle Bit
Figure 6,
S29AL008D_00A3 June 16, 2005