SCC1300-D02 VTI Technologies, SCC1300-D02 Datasheet - Page 17

• Manufacturer Part Number: SCC1300-D02
• Description: GYRO/ACC COMBO 3-AXIS +/-2G SPI
• Manufacturer: VTI Technologies

Specifications of SCC1300-D02

• Output Type: Digital - SPI
• Sensor Type: Gyroscope and Accelerometer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 551-1068-2

4.4.1.1
4.4.1.2
VTI Technologies Oy
www.vti.fi
Register read operation
Decremented register read operation
An example of X-axis acceleration read command is presented in Figure 9. Master gives the
register address to be read via MOSI_A line: '05' in hex format and '000101' in binary format,
register name is X_MSB (X-axis MSB frame). 7
8
The sensor replies to asked operation by transferring the register content via MISO_A line. After
transferring the asked X_MSB register content, master gives next register address to be read: '04'
in hex format and '000100' in binary format, register name is X_LSB (X-axis LSB frame). The
sensor replies to asked operation by transferring the register content MSB first.
Figure 9: Example of 16 bit acceleration data transfer from registers DOUT2-1 (05h,04h).
DO15…DO0 bits are acceleration data bits (DO15=MSB) and parity (dPAR) is odd parity of register
of 8 data bits. FRME is possible frame error bit of previous frame, PORST is reset bit, ST is self-
test status bit and SAT is output saturation status bit.
In Figure 10 is presented a decremented read operation where the content of four output registers
is read by one SPI frame. After normal register addressing and one register content reading the µC
keeps CSB_A line low and continues supplying the SCK_A pulses. After every 8 SCK pulses the
output data address is decremented by one and the previous DOUT register's content is shifted out
without parity bits. Parity bit is calculated and transferred only for the first data frame. From X_LSB
register address the ASIC jumps to Z_MSB. Decremented reading is possible only for registers
X_LSB ... Z_MSB.
Decremented read is not recommended in fail-safe critical applications because output data parity
is only available for first 8bit data.
Figure 10: An example of decremented read operation.
th
bit is 1 for odd parity.
Doc.Nr. 82 1130 00 A
Subject to changes
th
bit is set to '0' to indicate the read operation and
SCC1300-D02
Rev. 1.0
17/30