LMH0394SQ/NOPB National Semiconductor, LMH0394SQ/NOPB Datasheet - Page 12

• Manufacturer Part Number: LMH0394SQ/NOPB
• Description: IC EQUALIZER CABLE 16-LLP
• Manufacturer: National Semiconductor

Specifications of LMH0394SQ/NOPB

• Applications: Amplifier
• Interface: SPI Serial
• Voltage - Supply: 2.5V
• Package / Case: *
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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SPI Daisy-Chain Read
Figure 9
N devices. The SPI daisy-chain read is 32xN bits long, con-
sisting of 16xN bits for the read transaction followed by 16xN
bits for the dummy read transaction (all “1”s) to shift out the
read data on the MISO output. The SS signal is driven low
and SCK is toggled for 16xN clocks. The first 16xN bit MOSI
payload (sent to Device 1 in the daisy-chain) consists of the
16-bit SPI read data for Device N (the last device in the chain),
followed by the read data for Device N-1, Device N-2, etc.,
SPI Daisy-Chain Read and Write Example
The following example further clarifies LMH0394 SPI daisy-
chain operation. Assume a daisy-chain of three LMH0394
devices (Device 1, Device 2, and Device 3), with Device 1 as
the first device in the chain and Device 3 as the last device in
the chain, as shown by the first three devices in
Since there are three devices in the daisy-chain, each SPI
transaction is 48-bits long.
This example shows an SPI operation combining SPI reads
and writes in order to accomplish the following three tasks:
The following occurs at the end of the first transaction:
1.
Write 0x22 to register 0x01 of Device 1.
shows the SPI daisy-chain read for a daisy-chain of
FIGURE 10. SPI Daisy-Chain Read and Write Example
FIGURE 9. SPI Daisy-Chain Read
Figure
7.
12
ending with the read data for Device 1 (the first device in the
chain). The 16-bit SPI read data for each device consists of
a “1” (read command), seven address bits, and eight “1”s
(which are ignored). After the first 16xN bit transaction, SS
must return high (to latch the data) and then is driven low
again before the second 16xN bit transaction of all “1”s is sent
to the MOSI input. The requested read data is shifted out on
MISO starting with the data for Device N and ending with the
data for Device 1. After this transaction, SS must return high.
1.
2.
3.
Figure 10
complete these tasks (the bits are shifted in left to right).
2.
3.
Write 0x22 to register 0x01 of Device 1 in order to set the
output swing to 400 mV
Read the contents of register 0x00 of Device 2.
Write 0x10 to register 0x00 of Device 3 in order to force
the sleep mode.
Latch the data from register 0x00 of Device 2.
Write 0x10 to register 0x00 of Device 3.
shows the two 48-bit SPI transactions required to
P-P
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