83698 SENSONOR TECHNOLOGIES AS, 83698 Datasheet - Page 8

• Manufacturer Part Number: 83698
• Description: IC, SENSOR, PRESSURE, COMP, SP100-1
• Manufacturer: SENSONOR TECHNOLOGIES AS

Specifications of 83698

• Operating Temperature Range: -40°C To +125°C
• Pressure Type: Absolute
• Ic Generic Number: SP100-1
• No. Of Pins: 14
• Operating Pressure Range: 0 To 100kPa
• Sensor Case Style: SOIC
• Supply Voltage: RoHS Compliant
• Rohs Compliant: Yes

6.1
TS1483 rev. 1
When NCS is high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a high impedance
state.
During the NCS high-to-low transition, the SPI response word is multiplexed from the latch(es) that was(were)
defined by the last command present in the shift register. The SCLK pin must be low when NCS goes low.
At each clock rising edge after NCS has gone low, the response word is serially shifted out of the ASIC at the
SDO pin, LSB first. At each clock falling edge after NCS has gone low, the new control word is serially shifted into
the ASIC at the SDI pin, LSB first.
The command bits of the received SPI word are then decoded to determine the destination address for the data
bits. After the 8
stored in the ASIC SPI shift register to be transferred into the latch which address was decoded from the SPI shift
register command bits.
If the number of clock pulses before NCS goes high is different from 0, 8 or 16, a digital filter prevents execution of
the received command (A valid NCS pulse with 0 clock pulses will cause the previous command to be executed
again).
The Failure Status Indicator (FSI) is the logical OR of all bits in the status register, except bit 6.
The FSI appears at the SDO pin after NCS has gone low and before SCLK goes high (see timing diagram).
Table 6.1 SPI timing diagram
The FSI is valid only in response bytes that contain a measurement result value. If FSI is high, at least one of the
error bits in the status byte has been set, and the measurement result should be rejected.
Control bytes and response bytes are 8 bits, the content of which depends upon the command given. When a
control byte is shifted in, the response byte that is shifted out during the same transition time will be the response
byte from the previous command: Shift in control byte « n », shift out response byte « n - I ». Therefore, each
control/response pair requires two full 8-bit shift cycles to complete. The control bytes are described in chapter
6.2. Some control bytes require an additional data byte. For such command, the data byte must be transmitted
first, before the command byte.
SPI Protocol
th
clock falling edge has occurred, the following NCS low-to-high transition causes the data bits
DATASHEET
SP100 PRESSURE SENSOR SERIES
- 8 -
SP100-1(T), SP100-2(T)