83713 SENSONOR TECHNOLOGIES AS, 83713 Datasheet - Page 10

• Manufacturer Part Number: 83713
• Description: IC, SENSOR, PRESSURE, COMP, SP300-1
• Manufacturer: SENSONOR TECHNOLOGIES AS

Specifications of 83713

• Operating Temperature Range: -40°C To +125°C
• Pressure Type: Absolute
• Ic Generic Number: SP300-1
• No. Of Pins: 14
• Operating Pressure Range: 0kPa To 100kPa
• Sensor Case Style: SOIC
• Supply Voltage: RoHS Compliant
• Rohs Compliant: Yes

5.2
The SP300 employs a low-power RISC (Reduced Instruction Set Computing) controller to control device operation
according to an application program. The RISC is clocked from an on-chip RC oscillator, while the peripheral unit
Timer/Counter 0 may be clocked from an external source, for example the reference clock of a PLL chip in case a
higher precision or synchronous timing is desired.
The RISC features an 8 bit Harvard architecture with 16 bit instructions. Due to a two-stage pipeline concept the
instructions execute in a single instruction cycle, featuring fast execution time and low-power consumption. The RISC
block diagram is shown in Figure 6.3.
Byte-wise read access for the Application Program Memory is provided, whereas the firmware is not visible to the
application program due to the implemented shadow mechanism. A software interrupt (SYS) allows the execution of
library functions in ROM. The SYS mechanism handles the transition to the “shadowed” ROM.
The RISC features 128 byte of internal Data Memory. The Data Memory is also used as 16-bit program stack during
subroutine calls and interrupts. Although no specific instructions are provided to manipulate this stack (e.g. Push/Pop),
the RISC features auto-increment and auto-decrement addressing modes to enable data stack handling by the
application program.
Peripherals of the RISC (timer, I/O, etc) are accessible via a Special Function Register File (SFR) that is mapped into
the Data Address Space. The RISC allows byte-oriented as well as bit wise access to both Data Memory and SFR’s.
Eight general purpose registers (8 bit) are provided. Four of them may be used in the context of indirect addressing.
Two of these registers provide additional post-increment and pre-decrement addressing modes in order to support e.g.
a software data stack.
The ALU (Arithmetic Logic Unit)
supports instructions for
arithmetic, logical and Boolean
data manipulation.
The single priority level Interrupt
Control system features an
additional wakeup function from
IDLE mode, which provides the
application program with a
convenient means to synchronize
with the peripherals. A number of
special loop control and bit shift
instructions are available to
optimize code speed and size.
TS1488 rev. 1
RISC controller
DATASHEET
Figure 5.3 SP300 RISC controller block diagram
from Instr. Decoder
data memory
Interrupt Controller
Data Bit Pointer
BITMASK
Stack Pointer
USER
Register File
space
Stack
PSW
SP300 PRESSURE SENSOR SERIES
- 10 -
(R0, R1, R2, R3)
LSByte
MSByte
Decrement
Increment
R0
Unit
R1
SP DBP
B-Bus (8 bit)
A-Bus (8 bit)
PC
SP300-1(T), SP300-2(T)
R2
R3
ALU
Instr [6:0]
Program
Memory
(ROM)
data memory
Decoder
internal
Adr.
space
Instruction Bus (16 bit)
Instruction
Decoder
Data Bus (8 bit)
Data Address Bus (write)
Data Address Bus (read)