ADS-117MC Murata Power Solutions Inc, ADS-117MC Datasheet - Page 3

• Manufacturer Part Number: ADS-117MC
• Description: Analog To Digital Converter
• Manufacturer: Murata Power Solutions Inc

FUNCTIONAL SPECIFICATIONS. CONT.
DATEL
1. Applications which are unaffected by endpoint errors or remove them
2. Always connect the analog and digital grounds to a ground plane
3. Bypass the analog and digital supplies and the +10V reference (pin 21)
4. Obtain straight binary/offset binary output coding by tying COMP BIN
Operating Temp. Range, Case
Storage Temperature Range
Thermal Impedance
Package Type
Weight
TECHNICAL NOTES
ADS-117MC
ADS-117ME
ADS-117MM, 883
θjc
θca
through software will use the typical connections shown in Figure 3.
Remove system errors or adjust the small initial errors of the ADS-117
to zero using the optional external circuitry shown in Figure 4. The
external adjustment circuit has no effect on the throughput rate.
beneath the converter for best performance. The analog and digital
grounds are not connected to each other internally.
to ground with 4.7μF, 25V tantalum electrolytic capacitors in parallel
with 0.1μF ceramic capacitors. Bypass the +10V reference (pin 21) to
ANALOG GROUND (pin 23).
(pin 18) to +5V or leaving it open. The device has an internal pull-up
resistor on this pin. To obtain complementary binary or complementary
offset binary output coding, tie pin 18 to ground. The pin 18 signal
®
INTERNAL S/H
CONVERT
OUTPUT
PHYSICAL/ENVIRONMENTAL
START
DATA
EOC
Note: Scale is approximately 25ns per division.
–45
–55
–65
—
—
0
24-pin, metal-sealed, ceramic DDIP
0.42 ounces (12 grams)
DATA N-1 VALID
N
—
23
—
—
—
®
3
350ns min.
• 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: [phone] • www.datel.com • e-mail: [e-mail]
10ns min.
25ns max.
+125
+150
+70
+85
—
—
10ns min.
17ns max.
50ns typ.,
30ns min., 60ns max.
Conversion Time
Hold
325ns typ.
Figure 2. ADS-117 Timing Diagram
°C/W
°C/W
°C
°C
°C
°C
150ns max.
INVALID
DATA
Acquisition Time
170ns max.
165ns typ.
5. To enable the three-state outputs, connect ENABLE (pin 17) to a logic
6. To meet the guaranteed conversion rate, a maximum start convert pulse
7. Re-initiating the START CONVERT (pin 16) while EOC is a logic "1" (high)
12-Bit, 2MHz, Low-Power Sampling A/D Converters
is compatible with CMOS/TTL logic levels for those users desiring
dynamic control of this function. Do not change COMP BIN status while
EOC is high.
"0" (low). To disable, connect pin 17 to a logic "1" (high).
is specifi ed. A wider start convert pulse will result in slower conversion
rates. An initial start convert pulse is required before performing an
actual conversion after power-up to assure the sample-hold is in the
acquisition mode.
Figure 2 shows the relationship between the various input signals. The
timing shown applies over the operating temperature range and over
the operating power supply range.
will result in a new conversion sequence.
60ns max.
35ns max.
N+1
DATA N VALID
31 Mar 2011 MDA_ADS-117.B02 Page 3 of 6
INVALID
DATA
ADS-117