ADS-119MM Murata Power Solutions Inc, ADS-119MM Datasheet - Page 3

• Manufacturer Part Number: ADS-119MM
• Description: Analog To Digital Converter
• Manufacturer: Murata Power Solutions Inc

TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-119
2. The ADS-119 achieves its specified accuracies without the
Logic Levels
Output Coding
Power Supply Ranges
Power Supply Current
Power Dissipation
Power Supply Rejection
DIGITAL OUTPUTS
POWER REQUIREMENTS
Footnotes:
requires careful attention to pc-card layout and power
supply decoupling. The device's analog and digital ground
systems are connected to each other internally. For optimal
performance, tie all ground pins (14, 18, and 23) directly to
a large analog ground plane beneath the package.
Bypass all power supplies to ground with 4.7µF tantalum
capacitors in parallel with 0.1µF ceramic capacitors. Locate
the bypass capacitors as close to the unit as possible.
need for external calibration. If required, the device's small
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
+5V Supply
–5V Supply
+5V Supply
–5V Supply
®
All power supplies must be on before applying a start convert pulse. All supplies
and the clock (START CONVERT) must be present during warmup periods. The
device must be continuously converting during this time. There is slight
degradation in performance when using ±12V supplies.
See ordering information for availability of ±5V input range. Contact DATEL for
availability of other input voltage ranges.
A 200ns wide start convert pulse is used for all production testing. Only the rising
edge of the start convert pulse is required for the device to operate
(edge-triggered).
INTERNAL EOC
INTERNAL S/H
CONVERT
START
VALID
DATA
DATA
®
Scale is approximately 5ns per division.
INVALID DATA
+4.75
–4.75
MIN.
+2.4
—
—
—
—
—
—
—
50ns typ.
N
10ns typ.
15ns typ.
65ns typ.
Hold
DATA N-1 VALID
+25°C
Conversion Time
TYP.
+200
–180
+5.0
–5.0
1.8
55ns typ.
—
—
—
—
—
40ns typ.
35ns typ.
10ns typ.
Figure 2. ADS-119 Timing Diagram
±5ns
MAX.
+5.25
±0.01
–5.25
+215
–205
+0.4
2.1
—
–4
+4
Acquisition Time
37ns max.
30ns min.
35ns typ.
INVALID DATA
45ns typ.
60ns typ.
3
+4.75
–4.75
+2.4
MIN.
20ns typ.
—
—
—
—
—
—
—
3. Applying a start convert pulse while a conversion is in
4. Data is valid only for the time period (55ns, typical) shown in
Effective bits is equal to:
This is the time required before the A/D output data is valid after the analog input
is back within the specified range.
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figures 3 and 4. For
operation without adjustment, tie pin 17 to analog ground.
When using this circuitry, or any similar offset and gain-
calibration hardware, make adjustments following warmup.
To avoid interaction, always adjust offset before gain.
progress (EOC = logic "1") will initiate a new and inaccurate
conversion cycle.
Figure 2 even if the device is sampling at less than 10MHz.
N+1
0 to +70°C
Hold
+200
TYP.
–180
DATA N VALID
+5.0
–5.0
1.8
—
—
—
—
—
83ns max.
40ns typ.
72ns min.
80ns typ.
±5ns
(SNR + Distortion) – 1.76 +
Offset Binary
MAX.
+5.25
–5.25
±0.01
+215
–205
+0.4
2.1
–4
+4
—
INVALID DATA
+2.4
+4.9
–4.9
MIN.
—
—
—
—
—
—
—
–55 to +125°C
6.02
20 log
+200
–180
TYP.
+5.0
–5.0
1.8
—
—
—
—
—
Actual Input Amplitude
Full Scale Amplitude
+5.25
±0.01
–5.25
+215
–205
+0.4
MAX.
2.1
ADS-119
—
–4
+4
%FSR/%V
UNITS
Watts
Volts
Volts
Volts
Volts
mA
mA
mA
mA