ADS-932MM Murata Power Solutions Inc, ADS-932MM Datasheet - Page 4

• Manufacturer Part Number: ADS-932MM
• Description: Analog To Digital Converter
• Manufacturer: Murata Power Solutions Inc

INTERNAL FIFO OPERATION
The ADS-932 contains an internal, user-initiated, 18-bit, 16-word FIFO
memory. Each word in the FIFO contains the 16 data bits as well as the MSB
and OVERFLOW bits. Pins 23 (FIFO/DIR) and 10 (FIFO READ) control the FIFO's
operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1)
and 11 (FSTAT2).
When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the
digital data path. When pin 8 has a logic "0" applied, the FIFO is transpar-
ent, and the output data goes directly to the output three-state register (whose
operation is controlled by pin 34 (ENABLE). Read and write commands to the
FIFO are ignored when the ADS-932 is operated in the "direct" mode. It takes a
maximum of 20ns to switch the FIFO in or out of the ADS-932's digital data path.
FIFO WRITE and READ Modes
Once the FIFO has been enabled (pin 8 high), digital data is automatically
written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO
is initially empty, it will accept data (18-bit words) from the next 16 consecu-
tive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ
function) should not be low when data is fi rst written to an empty FIFO.
When the FIFO is initially empty, digital data from the fi rst conversion (the
"oldest" data) appears at the output of the FIFO immediately after the fi rst
conversion has been completed and remains there until the FIFO is read.
If the output three-state register has been enabled (logic "0" applied to pin
34), data from the fi rst conversion will appear at the output of the ADS-932.
Attempting to write a 17th word to a full FIFO will result in that data, and any
subsequent conversion data, being lost.
DATEL
®
DELAY
Direct mode to FIFO enabled
FIFO enabled to direct mode
FIFO READ to output data valid
FIFO READ to status update when changing
from <half full (1 word) to empty
FIFO READ to status update when changing
from half full (8 words) to <half full (7 words)
FIFO READ to status update when changing
from full (16 words) to half full (15 words)
Falling edge of EOC to status update when writing
first word into empty FIFO
Falling edge of EOC to status update when
changing FIFO from <half full (7 words) to
Falling edge of EOC to status update when filling
FIFO with 16th word
half full (8 words)
®
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PIN
32
32
32
8
8
9
9
9
9
Table 1. FIFO Delays
TRANSITION
1
1
1
0
1
0
0
0
1
Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both equal to "1"), it
can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then
applying a series of 15 rising edges to the read line. Since the fi rst data word
is already present at the FIFO output, the fi rst read command (the fi rst rising
edge applied to FIFO READ) will bring data from the second conversion to the
output. Each subsequent read command/rising edge brings the next word
to the output lines. After the 15th rising edge brings the 16th data word to
the FIFO output, the subsequent falling edge on READ will update the status
outputs (after a 20ns maximum delay) to FSTAT1 = 0, FSTAT2 = 1 indicating
that the FIFO is empty.
If a read command is issued after the FIFO empties, the last word (the 16th
conversion) will remain present at the outputs.
FIFO Reset Feature
At any time, the FIFO can be reset to an empty state by putting the ADS-932
into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying
a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be
indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status
outputs change 40ns after applying the control signals.
FIFO Status, FSTAT1 and FSTAT2
Monitor the status of the data in the FIFO by reading the two status pins,
FSTAT1 (pin 10) and FSTAT2 (pin 11).
1
1
1
1
0
0
0
0
0
CONTENTS
Empty (0 words)
<half full (≤7 words)
half-full or more (≥8 words)
Full (16 words)
16-Bit, 2 MHz Sampling A/D Converters
MIN.
–
–
–
–
–
–
–
–
–
TYP.
10
10
–
–
–
–
–
–
–
FSTAT1
0
0
1
1
MDA_ADS-932.B03 Page 4 of 9
MAX.
110
190
190
110
20
20
40
20
28
FSTAT2
ADS-932
1
0
0
1
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns