FAN6921MLMY Fairchild Semiconductor, FAN6921MLMY Datasheet
FAN6921MLMY
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FAN6921MLMY Summary of contents
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... Applications AC/DC NB Adapters Open-Frame SMPS Battery Charger Ordering Information Part Number OLP Mode FAN6921MLMY Latch © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Description The highly integrated FAN6921ML combines a Power Factor Correction (PFC) controller and a Quasi- Resonant PWM controller. Integration provides cost- effect design and allows for fewer external components ...
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... Application Diagram © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Figure 1. Typical Application 2 www.fairchildsemi.com ...
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... CSPWM Over Power Compensation t OFF-MIN (8us/37µs/2.5ms) t OFF S/H Blanking (4µs) 10 DET I 5V DET Internal OTP 9 GND © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0 RANGE OVP I HV OVP 2.75V 2.9V 27.5V Latched UVP Debounce 70µs 0.45V Latched Brownout Sawtooth ...
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... Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting 4 CSPFC protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal threshold (0.6 typical), the PFC switch is turned off to activate cycle-by-cycle current limiting. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 - Fairchild Logo Z - Plant Code ...
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... PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired connection High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100kΩ t ypical for providing a high-charging current to V © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 capacitor www.fairchildsemi.com ...
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... The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Parameter (3) (3) Parameter 6 Min ...
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... Low V Threshold for RANGE VIN V VIN-RANGE-L Comparator t Range-Enable/Disable Debounce Time RANGE Output Low Voltage of RANGE V RANGE-OL Pin t PFC Maximum On Time ON-MAX-PFC © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 ), unless otherwise specified. J Conditions 0.16V, DD DD-ON Gate Open V =15V, OPFC; DD OPWM=100KHz; C ...
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... PFC Current Sense Section Threshold Voltage for Peak V CSPFC Current Cycle-by-Cycle Limit t Propagation Delay PD t Leading-Edge Blanking Time BNK A CSPFC Compensation Ratio for THD V © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 (Continued) ), unless otherwise specified. J Conditions (4) RANGE=Open RANGE=Ground INVH REF ...
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... Bias Current Zero Duty-Cycle Input Voltage OZ V Open-Loop Protection Threshold Voltage FB-OLP t The Debounce Time for Open-Loop Protection FB-OLP t Internal Soft-Start Time FB-SS © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 (Continued) ), unless otherwise specified. J Conditions V = 25V DD V =15V, I =100mA ...
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... PFC OFF Debounce Time to t PFC-OFF Disable PFC t Inhibit Time During t INHIB-PFC-OFF PFC ON Debounce Time to t PFC-ON (4) Enable PFC t Start Timer (Time-Out Timer) STARTER-PWM © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 (Continued) ), unless otherwise specified. J Conditions (4) V =0V DET I =-1mA DET I =1mA ...
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... RT-RE-LATCH Threshold Voltage for Two-level V RT-OTP-LEVEL Debounce Time t Debounce Time for OTP RT-OTP-H Debounce Time for Externally t RT-OTP-L Triggering Note: 4. Guaranteed by design. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 (Continued) ), unless otherwise specified. J Conditions V = 25V 15V, Io=100mA 15V, Io=100mA DD ...
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... Temperature( ° C) Figure 9. Startup Current 2.60 2.55 2.50 2.45 2.40 -40 -25 - Temperature(°C) Figure 11. PFC Output Feedback Reference Voltage © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 =25° 110 125 110 125 Figure 110 125 110 125 Figure 12 ...
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... Temperature(°C) Figure 17. Beginning of Green-On Mode at V 9.0 8.5 8.0 7.5 7.0 -40 -25 - Temperature(°C) Figure 19. PWM Minimum Off Time for V © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 (Continued) =25° 110 125 Figure 14. PFC Peak Current Limit Voltage 110 125 ...
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... Temperature(°C) Figure 21. Lower Clamp Voltage of DET Pin 110.0 105.0 100.0 95.0 90.0 -40 -25 - Temperature(°C) Figure 23. Internal Source Current of RT Pin © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 (Continued) =25° 110 125 110 125 Figure 24. Over-Temperature Protection Threshold 14 2 ...
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... PFC MOS and the shape of the inductor current are shown in Figure 27. Figure 28 shows the difference between calculated fixed on time and fixed on time with THD optimizer during a half AC cycle. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 and R . When PFC ...
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... Even if the ZCD signal has been OFF detected, the PFC gate signal is not sent during the inhibit time (2.5µs typical). Figure 30. Internal Block of the Zero-Current Detection © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 V ZCD 10V voltage level VIN 2 ...
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... Until V higher than 1.2V (typical) and V voltage again, the PWM and PFC gate is sent out. The measured waveforms of brownin/out protection are shown in Figure 35. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Figure 34. Operation Waveforms of Brownin/out VIN V ...
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... FB voltage), the internal valley OFF-MIN detection circuit is activated to detect the valley on the drain voltage of the PWM switch. When the valley signal © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 is detected, FAN6921ML outputs PWM gate signal to turn on the switch and begin a new switching cycle. ...
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... DET can depend on this current I DET regulate the current limit level of the PWM switch to perform high / low line over-power compensation. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 As the input voltage increases, the reflected voltage on the auxiliary winding, V the current I a lower level ...
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... NTC R 0.5V RT Figure 43. Adjustable Over-Temperature Protection © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Output Over-Voltage Protection (DET Pin) Referring to Figure 44, during the discharge time of PWM transformer inductor; the voltage across on auxiliary winding is reflected from secondary winding and therefore the flat voltage on the DET pin is proportional to the output voltage ...
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... When the FB pin voltage is higher than 4.2V for 50ms, the FB pin protection is activated. Figure 45. FB Pin Open-Loop, Short Circuit, and Overload Protections © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Under-Voltage Lockout (UVLO, VDD Pin) Referring to Figure 36 and Figure 37, the turn-on and ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 23 www.fairchildsemi.com ...