ACMD-7403-TR1 Avago Technologies US Inc., ACMD-7403-TR1 Datasheet - Page 8

• Manufacturer Part Number: ACMD-7403-TR1
• Description: Duplexer, FBAR, US PCS
• Manufacturer: Avago Technologies US Inc.
• Series: -r

Specifications of ACMD-7403-TR1

• Frequency Bands (low / High): 1.85GHz ~ 1.9GHz / 1.93GHz ~ 1.99GHz
• Low Band Attenuation (min / Max Db): 52.00dB / -
• High Band Attenuation (min / Max Db): 40dB / -
• Return Loss (low Band / High Band): 17dB / 16dB
• Mounting Type: Surface Mount
• Package / Case: 3-CSP
• Screening Level: Commercial
• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

0.25 0.30
0.35
Notes:
1. Dimensions in mm
2. Transmission line Gap (G) adjusted for Zo = 50 ohms
3. I/O Pads (3 ea) 0.35 X 0.35, corner chamfer 0.03
4. Ground vias positioned to maximize port-to-port isolation
5. Preferred Tx connection on buried metal layer
Figure 19. PCB Layout
Figure 21. Recommended Solder Mask
A PCB layout using the principles illustrated in Figure 19
is recommended to optimize performance of the ACMD-
7403.
It is particularly important to maximize isolation between
the Tx connection to the duplexer and the Rx port. High
isolation is achieved by: (1) maintaining a continuous
ground plane around the duplexer mounting area, (2)
surrounding the I/O ports with sufficient ground vias to
enclose the connections in a “Faraday cage”, and (3) pref-
erably routing the Tx trace in a different metal layer than
the Rx.

0.45
0.20
G
G
0.45
Tx
0.35
2.90
0.20
0.25
0.30
2.10
Ant
> 0.30
> 0.30
TYP
TYP
2.90
Ø 0.30 VIA ARRAY
HORIZ PITC H = 0.40
VERT PITC H = 0.40
Rx
2.28
Figure 20. ACMD-7403 Superposed on PCB Layout
Figure 22. ACMD-7403 Superposed on Solder Mask
The latter is especially useful, not only to maintain Tx-Rx
isolation of the duplexer, but also to prevent leakage of
the Tx signal into other components that could result in
the creation of intermodulation products and degrada-
tion of overall system performance.
A sufficient number of vias should be used to ensure
excellent RF grounding as well as good heat sinking for
the device.
Note:
The two signal vias shown in Fig 17 are covered with solder mask and it
is not necessary to void the ground plane under them.