ACPL-C784-500E Avago Technologies US Inc., ACPL-C784-500E Datasheet - Page 8
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ACPL-C784-500E
Manufacturer Part Number
ACPL-C784-500E
Description
IC,Isolation Amplifier,SINGLE,SOP,8PIN,PLASTIC
Manufacturer
Avago Technologies US Inc.
Datasheet
1.ACPL-C784-500E.pdf
(17 pages)
Specifications of ACPL-C784-500E
Amplifier Type
Isolation
Number Of Circuits
1
Output Type
Differential
-3db Bandwidth
100kHz
Voltage - Input Offset
300µV
Current - Supply
11mA
Current - Output / Channel
18.6mA
Voltage - Supply, Single/dual (±)
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Slew Rate
-
Gain Bandwidth Product
-
Current - Input Bias
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ACPL-C784-500E
Manufacturer:
AVAGO/安华高
Quantity:
20 000
Notes:
General Note: Typical values represent the mean value of all char-
acterization units at the nominal operating conditions. Typical drift
specifications are determined by calculating the rate of change of the
specified parameter versus the drift parameter (at nominal operating
conditions) for each characterization unit, and then averaging the indi-
vidual unit rates. The corresponding drift figures are normalized to the
nominal operating conditions and show how much drift occurs as the
particular drift parameter is varied from its nominal value, with all other
parameters held at their nominal operating values. Note that the typical
drift specifications in the tables may differ from the slopes of the mean
curves shown in the corresponding figures.
1. It is recommended to operate with V
2. This is the Absolute Value of Input Offset Change vs. Temperature.
3. Gain is defined as the slope of the best-fit line of differential output
4. This is the Absolute Value of Gain Change vs. Temperature.
5. Nonlinearity is defined as half of the peak-to-peak output deviation
6. NL
7. The input supply current decreases as the differential input voltage
8. The maximum specified output supply current occurs when the
9. Because of the switched-capacitor nature of the input sigma-delta
10. When the differential input signal exceeds approximately 308 mV,
11. Short circuit current is the amount of output current generated when
Figure 1. Input Offset Voltage Test Circuit.
8
0.1 PF
V
If V
activated. This test mode is for LED coupling test and is not intended
for customer use.
voltage (V
the specified input range.
from the best-fit gain line, expressed as a percentage of the full-scale
differential output voltage.
±100 mV.
(V
differential input voltage (V
recommended operating input voltage. However, the output supply
current will continue to rise for differential input voltages up to
approximately –300 mV, beyond which the output supply current
remains constant.
converter, time-averaged values are shown.
the outputs will limit at the typical values shown.
either output is shorted to V
IN+
IN+
100
IN–
V
to 100 mV will improve DC nonlinearity and nonlinearity drift.
–V
DD1
is the nonlinearity specified over an input voltage range of
is brought above V
IN–
) decreases.
OUT+
–V
OUT–
1
2
3
4
) vs. differential input voltage (V
DD1
ACPL-C78A
ACPL-C780
ACPL-C784
DD2
IN+
– 2 V, an internal test mode may be
or GND2.
–V
IN–
IN–
) = –200 mV, the maximum
= 0 V (tied to GND1). Limiting
8
7
6
5
V
DD2
IN+
0.1 PF
10 K
10 K
–V
0.47
PF
IN–
) over
0.47
12. CMRR is defined as the ratio of the differential signal gain (signal
13. Output noise comes from two primary sources: chopper noise and
14. CMTI (Common Mode Transient Immunity or CMR, Common Mode
15. Data sheet value is the differential amplitude of the transient at the
16. In accordance with UL 1577, each optocoupler is proof tested by
17. The Input-Output Momentary Withstand Voltage is a dielectric
18. This is a two-terminal measurement: pins 1–4 are shorted together
PF
+
–
+15 V
applied differentially between pins 2 and 3) to the common-mode
gain (input pins tied together and the signal applied to both inputs
at the same time), expressed in dB.
sigma-delta quantization noise. Chopper noise results from chopper
stabilization of the output op-amps. It occurs at a specific frequency
(typically 400 kHz at room temperature), and is not attenuated by
the internal output filter. A filter circuit can be easily added to the
external post-amplifier to reduce the total RMS output noise. The
internal output filter does eliminate most, but not all, of the sigma-
delta quantization noise. The magnitude of the output quantization
noise is very small at lower frequencies (below 10 kHz) and increases
with increasing frequency.
Rejection) is tested by applying an exponentially rising/falling voltage
step on pin 4 (GND1) with respect to pin 5 (GND2). The rise time of
the test waveform is set to approximately 50 ns. The amplitude of the
step is adjusted until the differential output (V
more than a 200 mV deviation from the average output voltage for
more than 1μs. The ACPL-C78A/C780/C784 will continue to function
if more than 10 kV/μs common mode slopes are applied, as long as
the breakdown voltage limitations are observed.
output of the ACPL-C78A/C780/C784 when a 1 Vpk-pk, 1 MHz square
wave with 40 ns rise and fall times is applied to both V
applying an insulation test voltage ≥6000 Vrms for 1 second (leakage
detection current limit, I
100% production test for partial discharge (method b) shown in IEC/
EN/DIN EN 60747-5-2 Insulation Characteristic Table.
voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating, refer
to the IEC/EN/DIN EN 60747-5-2 insulation characteristics table and
your equipment level safety specification.
and pins 5–8 are shorted together.
-15 V
AD624CD
GAIN = 100
0.1 PF
0.1 PF
V
OUT
I-O
≤ 5 μA). This test is performed before the
OUT+
–V
DD1
OUT–
and V
) exhibits
DD2
.