LM3424BKBSTEVAL National Semiconductor, LM3424BKBSTEVAL Datasheet - Page 6

• Manufacturer Part Number: LM3424BKBSTEVAL
• Description: BOARD, EVALUATION, FOR LM3424BKBST
• Manufacturer: National Semiconductor

Specifications of LM3424BKBSTEVAL

• Kit Contents: Assembled LM3424 Buck-Boost Evaluation Board, Application Note, LM3424 Datasheet
• Svhc: No SVHC (15-Dec-2010)
• Kit Features: 1A Output, Thermal Foldback, Analogue Dimming, High Frequency
• Mcu Supported Families: LM3424

www.national.com
THERMAL SHUTDOWN
T
T
THERMAL RESISTANCE
θ
SD
HYS
JA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be
operated beyond such conditions. All voltages are with respect to the potential at the GND pin, unless otherwise specified.
Note 2: Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout wherein the
20L TSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation exists, namely driving a large MosFET
at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation
applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T
junction temperature (T
of the package in the application (θ
power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal resistances would be 104 °C/W
for the 20L TSSOP EP. It is possible to conservatively interpolate between the full via count thermal resistance and the no via count thermal resistance with a
straight line to get a thermal resistance for any number of vias in between these two limits.
Note 3: Refer to National’s packaging website for more detailed information and mounting techniques. http://www.national.com/analog/packaging/
Note 4: Human Body Model, applicable std. JESD22-A114-C.
Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used
to calculate Average Outgoing Quality Level (AOQL).
Note 6: Typical numbers are at 25°C and represent the most likely norm.
Note 7: These electrical parameters are guaranteed by design, and are not verified by test.
Note 8: The measurements were made using the standard buck-boost evaluation board from AN-1967.
Note 9: The measurements were made using the standard boost evaluation board from AN-1969.
Symbol
Thermal Shutdown
Threshold
Thermal Shutdown
Hysteresis
Junction to Ambient
J-MAX-OP
Parameter
= 125°C), the maximum power dissipation of the device in the application (P
JA
), as given by the following equation: T
(Note
(Note
20L TSSOP EP
7)
7)
Conditions
A-MAX
(Note
6
= T
J-MAX-OP
2)
– (θ
JA
× P
D-MAX
(Note
D-MAX
Min
A-MAX
). In most applications there is little need for the full
), and the junction-to ambient thermal resistance
5)
) is dependent on the maximum operating
(Note
Typ
165
25
34
6)
(Note
Max
5)
Units
°C/W
°C