AD9251-80EBZ Analog Devices Inc, AD9251-80EBZ Datasheet - Page 11

• Manufacturer Part Number: AD9251-80EBZ
• Description: 80MSPS ADC Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9251-80EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9251
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1.8 Vpp
• Power (typ) @ Conditions: 33mW @ 20 MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9251
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Description
Pin No.
0
1, 2
3
4, 5, 25, 26
6 to 9, 11 to 18, 20, 21
10, 19, 28, 37
22
23
24
27, 29 to 36, 38 to 42
43
44
45
46
47
48
49, 50, 53, 54, 59, 60, 63, 64
51, 52
Mnemonic
GND
CLK+, CLK−
SYNC
NC
D0B to D13B
DRVDD
ORB
DCOB
DCOA
D0A to D13A
ORA
SDIO/DCS
SCLK/DFS
CSB
OEB
PDWN
AVDD
VIN+A, VIN−A
(LSB) D0B
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
DRVDD
SYNC
CLK+
CLK–
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
NC
NC
10
12
13
14
15
16
11
Description
Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
Do Not Connect.
Channel B Digital Outputs. D13B = MSB.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
Channel A Digital Outputs. D13A = MSB.
Channel A Out-of-Range Digital Output.
SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-
down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.
SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal
pull-down.
DFS high = twos complement output.
DFS low = offset binary output.
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
Digital Input. Enable Channel A and Channel B digital outputs if low, tristate outputs if high.
30 kΩ internal pull-down.
Digital Input. 30 kΩ internal pull-down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
1.8 V Analog Supply Pins.
Channel A Analog Inputs.
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 5. Pin Configuration
Rev. A | Page 11 of 36
(Not to Scale)
AD9251
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D13A (MSB)
D12A
D11A
D10A
D9A
DRVDD
D8A
D7A
D6A
D5A
AD9251