AD9255-80EBZ Analog Devices Inc, AD9255-80EBZ Datasheet - Page 36

• Manufacturer Part Number: AD9255-80EBZ
• Description: A/D Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9255-80EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9255
• Kit Contents: Board
• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 239mW @ 80MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9255
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9255
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
transfer register (Address 0xFF); the ADC functions registers,
including setup, control, and test (Address 0x08 to Address 0x30);
and the digital feature control registers (Address 0x100).
The memory map register table (see Table 17) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading, Bit 7 (MSB), is the start of the
default hexadecimal value given. For example, Address 0x18, the
VREF select register, has a hexadecimal default value of 0xC0. This
means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This
setting is the default reference selection setting. The default value
uses a 2.0 V p-p reference. For more information on this function
and others, see AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This document details the functions controlled by
Register 0x00 to Register 0x30. The remaining register, at
Register 0x100, is documented in the Memory Map Register
Descriptions section.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
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valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
After the AD9255 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Logic Levels
An explanation of logic level terminology follows:
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•
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit. ”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit. ”