ADIS16220/PCBZ Analog Devices Inc, ADIS16220/PCBZ Datasheet - Page 9

• Manufacturer Part Number: ADIS16220/PCBZ
• Description: Vibration Sensor Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: iSensor™r

Specifications of ADIS16220/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Vibration Sensor
• Kit Application Type: Sensing - Motion / Vibration / Shock
• Silicon Core Number: ADIS16220
• Kit Contents: Board
• Sensor Type: Vibration, Accelerometer
• Sensing Range: ±70g
• Interface: SPI Serial
• Sensitivity: 19.073mg/LSB
• Voltage - Supply: 3.15 V ~ 3.6 V
• Embedded: No
• Utilized Ic / Part: ADIS16220
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BASIC OPERATION
The ADIS16220 uses a serial peripheral interface (SPI) for
communication, which enables a simple connection with a
compatible, embedded processor platform, as shown in Figure 9.
The two general-purpose lines provide options for a busy indica-
tor, an alarm indicator, a general-purpose input/output function,
and an external capture trigger input.
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
SS
IRQ1, IRQ2
MOSI
MISO
SCLK
The ADIS16220 SPI interface supports full duplex serial
communication (simultaneous transmit and receive) and uses
the bit sequence shown in Figure 13. Table 7 provides a list of
the most common settings that require attention to initialize a
processor’s serial port for the ADIS16220 SPI interface.
Table 7. Generic Master Processor SPI Settings
Processor Setting
Master
SCLK Rate ≤ 2.25 MHz
SPI Mode 3 (1, 1)
MSB-First
16-Bit
The user registers in Table 8 govern all data collection and
configuration. Figure 10 provides a generic bit assignment when
referencing each registers’ bit descriptions.
SYSTEM PROCESSOR
SPI MASTER
DOUT
SCLK
NOTES
1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
DIN
V
Figure 9. Electrical Hook-Up Diagram
CS
DD
Function
Slave select
Interrupt request inputs
Master output, slave input
Master input, slave output
Serial clock
SCLK
MOSI
MISO
IRQ1
IRQ2
DB15
SS
Description
ADIS16220 operates as a slave
Bit rate setting
Clock polarity/phase (CPOL = 1, CPHA = 1)
Bit sequence
Shift register/data length
R/W
DB14
A6
DB13
A5
4
1
3
2
5
6
CS
SCLK
DIN
DOUT
DIO1
DIO2
DB12
ADIS16220
A4
SPI SLAVE
DB11
VDD
A3
13
16
DB10
A2
Figure 13. Example SPI Read Sequence
DB9
A1
DB8
A0
Rev. 0 | Page 9 of 20
DB7
D7
DB6
D6
DB5
D5
SPI WRITE COMMANDS
The control registers in Table 8 provide configuration options for
a variety of functions. A master processor writes to the registers,
one byte at a time, using simple firmware commands and the bit
assignments in Figure 13. Because each byte in a register is
independent, some functions only require one write cycle. For
example, set GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a
manual capture sequence. The manual capture starts imme-
diately after the last bit clocks into DIN (16
SPI READ COMMANDS
A single register read requires two 16-bit SPI cycles, which also
use the bit assignments in Figure 13. The first sequence sets
R /W = 0 and communicates the target address (A6:A0). For a
read request, D7:D0 are don’t care bits. For simplicity, set D7:D0
equal to zero during read request commands. DOUT clocks out
during the second sequence. The second sequence can also use
DIN to setup the next read. Figure 12 provides a signal diagram
for all four SPI signals while reading the acceleration capture
buffer (CAPT_BUFA) in a repeating pattern. In this diagram,
DIN = 0x1400 and DOUT reflects the CAPT_BUFA register
contents.
DOUT
SCLK
SCLK
15
DIN
CS
DIN
CS
DB4
D4
Figure 11. SPI Sequence for Manual Capture Start (DIN = 0xBF08)
14
DOUT = 1111 1001 1101 1010 = 0xF9DA = –1573 LSBs ≥ –30.002g
DB3
D3
13
Figure 12. Example SPI Read, Second 16-Bit Sequence
UPPER BYTE
12
DB2
D2
Figure 10. Generic Register Bit Definitions
11
DB1
D1
10
DB0
D0
9
8
DIN = 0001 0100 0000 0000 = 0x1400
7
DB15
R/W
6
DB14
5
A6
LOWER BYTE
th
4
DB13
SCLK rising edge).
A5
ADIS16220
3
2
1
0