EVAL-AD7780EBZ Analog Devices Inc, EVAL-AD7780EBZ Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD7780EBZ
• Description: ADC Converter Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7780EBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7780
• Kit Contents: Board And Literature
• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 16.7
• Data Interface: SPI™
• Inputs Per Adc: 1 Differential
• Input Range: ±5 V
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: AD7780
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin No.
TSSOP
2
3
1, 4, 16
5
6
7
8
9
10
11
12
13
14
15
DOUT/RDY
REFIN(+)
Mnemonic
GAIN
FILTER
SCLK
DOUT/RDY
NC
AIN(+)
AIN(−)
REFIN(+)
REFIN(−)
BPDSW
GND
AV
DV
PDRST
AIN(+)
AIN(–)
SCLK
Figure 6. SOIC Pin Configuration
GAIN
NC
DD
DD
NC = NO CONNECT
1
2
3
4
5
6
7
(Not to Scale)
AD7780
TOP VIEW
Description
Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK pin has a Schmitt-
triggered input. The serial clock can be active only when transferring data from the AD7780. The data
from the AD7780 can be read as a continuous 32-bit word. Alternatively, SCLK can be noncontinuous
during the data transfer, with the information being transmitted from the ADC in smaller data batches.
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose: as a data ready pin, going low to
indicate the completion of a conversion, and as a serial data output pin to access the data register of the
ADC. Eight status bits accompany each data read (see
as an interrupt to a processor, indicating that new data is available. If the data is not read after the conver-
sion, the pin goes high before the next update occurs. The serial interface is reset each time that a conversion is
available. Therefore, the user must ensure that any conversions being transmitted are completed before
the next conversion is available.
No Connect. This pin can be left floating.
Gain Select Pin. When GAIN is low, the gain is set to 128. When GAIN is high, the gain is set to 1.
Analog Input. AIN(+) is the positive terminal of the differential analog input pair, AIN(+)/AIN(−).
Analog Input. AIN(−) is the negative terminal of the differential analog input pair, AIN(+)/AIN(−).
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). The nomi-
nal reference voltage (REFIN(+) − REFIN(−)) is 5 V, but the part can function with a reference of 0.5 V to AV
Negative Reference Input.
Bridge Power-Down Switch to GND. When PDRST is high, the bridge power-down switch is closed. When
PDRST is low, the switch is opened.
Ground Reference Point.
Supply Voltage, 2.7 V to 5.25 V.
Digital Interface Supply Voltage. The logic levels for the serial interface pins and the digital control pins
are related to this supply, which is between 2.7 V and 5.25 V. The DV
voltage on AV
Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode, and the low-side power
switch is opened. All the logic on the chip is reset, and the DOUT/RDY pin is tristated. When PDRST is high,
the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC
continuously converts. In addition, the low-side power switch is closed. The internal clock requires
approximately 1 ms to power up.
Filter Select. When FILTER is low, the fast settling filter is selected. The update rate is set to 16.7 Hz, which
gives a filter settling time of 120 ms. When FILTER is high, the high rejection filter is selected. The update
rate is set to 10 Hz, which gives a filter settling time of 300 ms. With this filter, the stop-band (higher than
f
ADC
) attenuation is better than −45 dB.
14
13
12
11
10
9
8
FILTER
PDRST
DV
AV
GND
BPDSW
REFIN(–)
DD
DD
DD
; therefore, AV
Rev. A | Page 7 of 16
DD
can equal 5 V with DV
Figure 22
DOUT/RDY
DD
REFIN(+)
AIN(+)
AIN(–)
at 3 V or vice versa.
SCLK
GAIN
Figure 7. TSSOP Pin Configuration
NC
NC
). The DOUT/
1
4
5
2
3
6
7
8
NC = NO CONNECT
(Not to Scale)
AD7780
TOP VIEW
DD
voltage is independent of the
RDY falling edge can be used
16
14
15
13
12
11
10
9
NC
FILTER
PDRST
DV
AV
GND
BPDSW
REFIN(–)
DD
DD
AD7780
DD
.