ADIS16135/PCBZ Analog Devices Inc, ADIS16135/PCBZ Datasheet - Page 11

• Manufacturer Part Number: ADIS16135/PCBZ
• Description: Precision Angular Rate Sensor Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of ADIS16135/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Angular Rate Sensor / Gyroscope
• Kit Application Type: Sensing - Motion / Vibration / Shock
• Silicon Core Number: ADIS16135
• Lead Free Status / RoHS Status: Lead free / RoHS non-compliant

DIGITAL PROCESSING CONFIGURATION
Figure 18 provides a block diagram for the sampling and digital
filter stages inside the ADIS16135. Table 15 provides a summary
of registers for sample rate and filter control.
Table 15. Digital Processing Registers
Register Name
SMPL_PRD
AVG_CNT
DEC_RATE
Internal Sample Rate
The SMPL_PRD register in Table 16 provides a programmable
control for the internal sample rate. Use the following formula
to calculate the decimal number for the code to write into this
register:
The factory default setting for SMPL_PRD sets the internal
sample rate to a rate of 1024 SPS; the minimum setting for the
SMPL_PRD register is 0x000F, which results in an internal
sample rate of 2048 SPS.
Table 16. SMPL_PRD Bit Descriptions
Bits
[15:0]
Input Clock Configuration
Set SMPL_PRD = 0x0000 (DIN = 0x9F00, then DIN = 0x9E00)
to disable the internal clock and enable CLKIN as a clock input pin.
Digital Filtering
The AVG_CNT register (see Table 17) provides user controls
for the low-pass filter. This filter contains two cascaded averaging
filters that provide a Bartlett window FIR filter response (see
Figure 18). For example, set AVG_CNT[7:0] = 0x04 (DIN =
0xA004) to set each stage to 16 taps. When used with the default
sample rate of 1024 SPS, this establishes a −3dB bandwidth of
approximately 20 Hz for this filter.
SMPL
Description (Default = 0x001F)
Clock setting bits; sets f
_
PRD
Address
0x1E
0x20
0x22
=
MEMS
GYRO
32
( )
,
f
768
S
–3dB BANDWIDTH = 335Hz
−
; 1
Description
Sample rate control
Digital filtering and range control
Decimation rate setting
402Hz
f
S
f
SP ≥ 15
SP = SMPL_PRD
S
S
≤
in Figure 18
=
2048
32,768
SP + 1
819Hz
SPS
Figure 18. Sampling and Frequency Response Block Diagram
CLOCK
CLKIN
f
S
Rev. B | Page 11 of 20
B = AVG_CNT[2:0]
N
N
B
B
= 2
= NUMBER OF TAPS PER STAGE
B
Table 17. AVG_CNT Bit Descriptions
Bits
[15:3]
[2:0]
Averaging/Decimation Filter
The DEC_RATE register (see Table 18) provides user control
for the final filter stage (see Figure 18), which averages and
decimates the output data. For systems that value lower sample
rates, this filter stage provides an opportunity to lower the sample
rate while maintaining optimal bias stability performance. The
−3 dB bandwidth of this filter stage is approximately one half
the output data rate. For example, set DEC_RATE[7:0] = 0x04
(DIN = 0xA204) to reduce the sample rate by a factor of 16.
When the factory default 1024 SPS sample rate is used, this
decimation setting reduces the output data rate to 64 SPS and
the sensor bandwidth to approximately 31 Hz.
Table 18. DEC_RATE Bit Descriptions
Bits
[15:5]
[4:0]
–100
–120
–140
–20
–40
–60
–80
0.001
Figure 17. Bartlett Window FIR Filter Frequency Response
0
Description (Default = 0x0000)
Don’t care
Binary; B variable in Figure 18; maximum = 110 (6)
Description (Default = 0x0000)
Don’t care
Binary; D variable in Figure 18; maximum setting =
1000 (binary) = 16 (decimal)
N = 2
N = 4
N = 16
N = 64
D = DEC_RATE[4:0]
N
N
N
D
D
D
(Phase Delay = N Samples)
= 2
= NUMBER OF TAPS
= DATA RATE DIVISOR
D
0.01
FREQUENCY (
÷N
f
/
f
S
D
)
0.1
ADIS16135
1