CDB5330A Cirrus Logic Inc, CDB5330A Datasheet - Page 3
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CDB5330A
Manufacturer Part Number
CDB5330A
Description
Development Kit
Manufacturer
Cirrus Logic Inc
Datasheet
1.CDB5330A.pdf
(14 pages)
Specifications of CDB5330A
Silicon Manufacturer
Cirrus Logic
Application Sub Type
ADC
Kit Application Type
Data Converter
Silicon Core Number
CS5330A
Features
Digital & Analog Patch Areas, Buffered Serial Output Interface
Product
Audio Modules
Kit Contents
Board
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
The transceiver operates as a transmitter with the
MASTER/SLAVE jumper in the MASTER posi-
tion. LRCK, SDATA, and SCLK from the
CS5330A/31A will be available on HDR2.
HDR22 must be in the 0 position and HDR23
must be in the 1 position for MCLK to be an
output and to avoid bus contention on MCLK.
The transceiver operates as a receiver with the
MASTER/SLAVE jumper in the SLAVE posi-
tion. LRCK and SCLK on HDR2 become inputs.
However, the recommended mode of operation is
to generate MCLK on the evaluation board with
HDR23 in the 0 position and HDR22 in the 1
position. These default settings allow MCLK to
be an output, with LRCK and SCLK as inputs.
MCLK is always an output from the evaluation
board.
DS138DB2
MCLK, SCLK, LRCK,
CONNECTOR
Optical Output
Digital Output
SDATA
AINR
GND
AINL
+5V
INPUT/OUTPUT
input/output
output
output
input
input
input
input
Table 1. System Connections
(VD+) for CS8402A and digital section
(VA+) for CS5330A/31A and Analog input filter op-amp
ground connection from power supply
left channel analog input
right channel analog input
I/O for master, serial, left/right clocks, and serial DATA
digital audio interface output via coax
digital audio interface output via optical
Grounding and Power Supply Decoupling
The CS5330A/31A requires careful attention to
power supply and grounding arrangements to op-
timize performance. Figure 2 shows the
recommended power arrangements. The
CS5330A/31A is positioned over the analog
ground plane, near the digital/analog ground
plane split, to minimize the distance that the
clocks travel. The series resistors are present on
the clock lines to reduce the effects of transient
currents when driving a capacitive load in master
mode, and reduce clock overshoot when apply-
ing external clocks to the CS5330A/31A in slave
mode.
This layout technique is used to minimize digital
noise and to insure proper power supply match-
ing/sequencing. The decoupling capacitors are
located as close to the CS5330A/31A as possi-
ble. Extensive use of ground plane fill on both
the analog and digital sections of the evaluation
board yield large reductions in radiated noise ef-
fects.
SIGNAL PRESENT
CDB5330A / CDB5331A
19