CDB5451 Cirrus Logic Inc, CDB5451 Datasheet

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CDB5451

Manufacturer Part Number
CDB5451
Description
Development Kit
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CDB5451

Silicon Manufacturer
Cirrus Logic
Application Sub Type
ADC
Kit Application Type
Data Converter
Silicon Core Number
CS5451
Features
RS-232 Serial Communication With PC, Noise Histogram Analysis, FFT Analysis
Kit Contents
Evaluation Board And Software
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
l
l
l
l
l
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Direct Shunt Sensor and Current
Transformer Interface for 3-Phase
Power
On-Board Voltage Reference
On-board crystal for XIN
Digital Interface to PC
Lab Windows/CVI Evaluation
Software
- “Real-Time” RMS calculation
- FFT Analysis
- Time Domain Analysis
- Noise Histogram Analysis
CDB5471 Evaluation Board and Software
V
VIN1+
VIN2+
VIN3+
VIN1-
VIN2-
VIN3-
IIN1+
IIN2+
IIN3+
REF
IIN1-
IIN2-
IIN3-
Reference
Voltage
IN
CPD
CS5451
V
RESET
REF
OWRS
Circuitry
GAIN
Charge
SDO
OUT
VA-
Pump
FSO
VA+
CLK
VA-
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
XIN
SE
VA+
Header
Copyright
General Description
The CDB5471 is an inexpensive tool designed to evalu-
ate the functionality/performance of the CS5471 2-
channel A/D Converter. In addition to this data sheet, the
CS5471 Data Sheet is required in conjunction with the
CDB5471 Evaluation Board.
Two terminal-block connectors serve as inputs to the
CS5471’s two analog input pairs. The CDB5471 in-
cludes an optional voltage reference source for CS5471.
A 4.096MHz crystal is provided as a source for CS5471’s
XIN pin, or an external clock source can be supplied by
the user. Digital output data from the CS5471 is trans-
ferred to the user’s IBM-compatible PC via the included
25-pin parallel port cable.
The CDB5471 includes PC software, allowing the user to
perform data capture (includes option for time domain
analysis, histogram analysis, and frequency domain
analysis). The software also allows real-time RMS calcu-
lation/analysis to be performed simultaneously on the
instantaneous data from both channels.
ORDERING INFORMATION
(Not Populated)
Regulator
+5 VIN
(All Rights Reserved)
CDB5471
3 V
Reset Circuit
4.096 MHz
Cirrus Logic, Inc. 2001
Crystal
Serial-to-
Interface
Parallel
Control Switches
GND
VD+
LK\
CDB5471
To PC
Evaluation Board
DS480DB1
FEB ‘01
1

Related parts for CDB5451

CDB5451 Summary of contents

Page 1

CDB5471 Evaluation Board and Software Features Direct Shunt Sensor and Current l Transformer Interface for 3-Phase Power On-Board Voltage Reference l On-board crystal for XIN l Digital Interface Lab Windows/CVI Evaluation l Software - “Real-Time” RMS calculation ...

Page 2

TABLE OF CONTENTS 1. INTRODUCTION ....................................................................................................................... 4 1.1 CS5471 .............................................................................................................................. 4 1.2 Data Flow on Evaluation Board ......................................................................................... 4 2. HARDWARE ............................................................................................................................. 5 2.1 Evaluation Board Description ............................................................................................. 5 2.2 Power Supply Connections ................................................................................................ 5 2.2.1 Analog Power Supply ............................................................................................ ...

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LIST OF FIGURES Figure 1. Power Supply, CS5471, and Oscillator .............................................. 11 Figure 2. Analog Inputs ..................................................................................... 12 Figure 3. Digital Circuitry ................................................................................... 13 Figure 4. Start-Up Window ................................................................................ 15 Figure 5. Conversion Window ........................................................................... 16 Figure 6. Data Collection ...

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... The user can save raw data from the CS5471 to a data file, which al- lows to user to analyze performance with other tools that may be preferable to the user. 1.1 CS5471 The CS5471 is a highly integrated Two-Channel Delta-Sigma Analog-to-Digital Converter (ADC) developed for power measurement/metering appli- cations ...

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HARDWARE 2.1 Evaluation Board Description The CDB5471 board contains circuitry that will: • Accept appropriate DC voltage levels from the user’s +3V and/or +5V power supplies, and direct this power to the VA+, VD+, VA- and DGND pins of ...

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CS5471 (VD+ pin), the 4.096 MHz oscillator (U1), and circuitry for the parallel port interface. This is controlled ...

Page 7

Name Function Description Used to switch IIN3+ on the CS5471 between J2 HDR1 and AGND. Used to switch VIN3- on the CS5471 between J3 HDR2 and AGND. Used to switch VIN3+ on the CS5471 between J1 HDR3 and AGND. Used ...

Page 8

Name Function Description HDR15 Controls the source for the CS5471 XIN clock input. HDR16 This header should always be shorted. Determines whether the main analog supply will be HDR17 powered from the A- post, or from the regulated 3V voltage ...

Page 9

CS5451 by obtaining a CS5451 sample and connect it in place of the CS5471 device. Then the remaining four input channels serve as the inputs to the CS5451’s four additional input pairs. Other header options listed in Table 2 ...

Page 10

The user should recall from CS5471 Data Sheet that the serial interface on the CS5471 device is a “master-mode” interface, which means that the de- vice provides the clock. Once the CS5471 is pow- ered on, the SCLK pin produces ...

Page 11

U5 +5V TP40 CON_BANANA LM317LZ TP77 3.0V +5V_IN IN OUT 3 2 ADJ J21 C40 C42 C39 Z4 1 P6KE6V8P .1UF 10UF .1UF GND C38 Do Not Populate .33UF TANT CON_BANANA GND J18 C20 GND .1UF +3V GND HDR17 V+ ...

Page 12

J22 TP67 HDR2X2 J5 R23 301 0.1% BNC_RA C8 GND 4700PF TP66 HDR2X2 J7 R22 301 0.1% BNC_RA GND TP65 HDR2X2 J6 R21 301 0.1% BNC_RA C7 GND 4700PF TP64 HDR2X2 J8 R24 301 0.1% BNC_RA GND GND TP4 HDR2X2 ...

Page 13

HDR7X2 HDR19 1 2 OWRS 3 4 /RESET 5 6 /GAIN FSO 11 12 SCLK 13 14 SDO GND D+ SW1 R35 10K /GAIN 2 R34 10K OWRS 1 SW_DIP_2 GND /RESET R36 20K D+ ...

Page 14

SOFTWARE The evaluation software was developed with Lab Windows/CVI , a software development package from National Instruments. The software is de- signed to run under Windows 95 or later, and re- quires about hard drive space ...

Page 15

The Start-Up Window When the software first executes, the user should see the Start-Up Window appear on the user’s PC monitor. This window is shown in Figure 4. From this window, the user can navigate to three other main ...

Page 16

The results that are displayed on this screen are therefore updated after each computation cycle. ...

Page 17

Last Value The first column is labelled as “Last Value.” The value in this box represents the value of the very last instantaneous sample that was taken (for both channels) in the most recently-completed computa- tion cycle. If the ...

Page 18

... Hz) when performing an FFT analysis. The user can enter the crystal frequency that is used on the CDB5451 board into this box. The default val this box is set for the on-board 4.096MHz os- cillator. 3.2.4.4. OWRS Pin Setting: ...

Page 19

Figure 7. Configuration Window 3.2.5.3. FFT Window This box allows the user to select the type of win- dowing algorithm for FFT processing. Windowing algorithms include the Blackman, Black-Harris, Hanning, 5-term Hodie, and 7-term Hodie. The 5- term Hodie and ...

Page 20

Minimum Indicator for the minimum value of the collected data set. 3.2.8 Frequency Domain Information The following section describes the indicators as- sociated with FFT (Fast-Fourier Transform) analy- sis. Refer to Figure 8. FFT data can be plotted in ...

Page 21

Histogram Information See figure 9. The following is a description of the indicators associated with Histogram Analysis. Histogram can plotted in the Data Collection Win- dow by setting the Time Domain / FFT / Histogram selector to “Histogram.” 3.2.9.1. ...

Page 22

Figure 10. Silkscreen CDB5471 DS480DB1 ...

Page 23

DS480DB1 Figure 11. Circuit Side CDB5471 23 ...

Page 24

Figure 12. Solder Side CDB5471 DS480DB1 ...

Page 25

Notes • ...

Page 26

...

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