CDB6420 Cirrus Logic Inc, CDB6420 Datasheet
CDB6420
Specifications of CDB6420
Related parts for CDB6420
CDB6420 Summary of contents
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... The CS6420 enables full-duplex conversation with a sin- gle-chip solution. The CS6420 can easily replace existing half-duplex speakerphone ICs with a huge in- crease in conversation quality. The CS6420 consists of telephone & audio interfaces, two codecs and an echo-cancelling DSP. ORDERING INFORMATION CS6420-CS CDB6420 NC3 NC2 NC1 AGND Acoustic Pre-Emphasis Echo Canceller ...
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Absolute Maximum Ratings ..............................................................................................4 Recommended Operating Conditions..............................................................................4 Power Consumption ..........................................................................................................4 Analog Characteristics ........................................................................................................4 Analog Transmission Characteristics..............................................................................5 Microphone Amplifier ........................................................................................................5 Digital Characteristics .......................................................................................................5 Overview ............................................................................................................................8 Functional Description .....................................................................................................8 Analog Interface .......................................................................................................8 Acoustic Interface ..............................................................................................9 Network Interface ............................................................................................10 Microcontroller Interface .........................................................................................10 Description ...
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Speech Detection ..................................................................................... 24 Half-Duplex Mode ........................................................................................... 24 AGC ................................................................................................................ 25 Suppression .................................................................................................... 25 Transmit Suppression............................................................................... 26 Receive Suppression ................................................................................ 27 Circuit Design ......................................................................................................... 27 Interface Considerations ................................................................................. 27 Analog Interface........................................................................................ 27 Microcontroller Interface ........................................................................... 27 Grounding Considerations .............................................................................. 28 ...
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ABSOLUTE MAXIMUM RATINGS Parameter DC Supply (AVDD, DVDD) Input Current (Except supply pins) Input Voltage Ambient Operating Temperature Storage Temperature WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these ...
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ANALOG TRANSMISSION CHARACTERISTICS 20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HD=TSD=RSD=1, analog inputs and ouputs loaded with resistors and capacitors as shown in the typical connection diagram, Figure 2) Parameter Idle Channel Noise (Inputs grounded C-Message weighted (0-4 kHz) through a capacitor) ...
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SWITCHING CHARACTERISTICS Parameter Input rise time RST low time CLKI frequency CLKI duty cycle DRDY frequency STROBE frequency DRDY to STROBE setup time DATA to STROBE setup time STROBE to DATA hold time STROBE to DRDY hold time DRDY STROBE ...
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12.1 k Telephone Line Out 3300 pF 0.47 F 6.04 k Telephone Line In 3300 pF From Microprocessor Figure 2. Typical Connection Diagram (Microphone Preamplifier Enabled) 0 12.1 k Telephone Line ...
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OVERVIEW The CS6420 is a full-duplex speakerphone chip for use in hands-free communications with telephony quality audio. Common applications include speakerphones, inexpensive video-conferencing, and cellular phone car kits. The CS6420 requires very few external components and allows system control through ...
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NI PGA ADC 17 0,6,9.5, DAC 4 FAR-END and they are post-compensated internally to pre- vent any resultant passband droop. The ADCs also expect a maximum (2.8 V rms puts (which are biased around 2.12 ...
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ADC input. The default gain stage setting is 0 dB. The signal at APO should not exceed 2.8 V default gain ...
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The next data bit should then be presented to the DATA pin ready to be latched by the rising edge of STROBE. This procedure repeats for all sixteen bits as shown ...
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Register 0 b15 b14 b13 b12 b11 Mic TSD Bits Name Function 15 Mic Microphone Preamplifier Enable 14 TSD Tx Suppression Disable 13-12 GB Graded Beta 11-10 ACC AEC Coefficient Control 9-5 RVol Rx Volume Control ...
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CS6420, is controlled by GB. The network echo canceller does not support graded beta. Graded beta is an architectural enhancement to the CS6420 which takes advantage of the fact that acoustic echoes tend to decay exponentially with time. The CS6420 ...
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Register 1 b15 b14 b13 b12 b11 HD RSD Taps Bits Name 15 HD Half-Duplex Disable 14 RSD Rx Suppression Disable 13-12 Taps AEC/NEC Tap Allocation 11-10 NCC NEC Coefficient Control 9-5 TVol 4-3 RGain * Denotes ...
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By default, the receive suppression function is enabled. Taps - AEC/NEC Tap Allocation The CS6420 has a total of 63 echo canceller taps that it can partition for use by the network and acoustic echo cancellers. ...
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Register 2 b15 b14 b13 b12 b11 NErle NFNse RHDet 00 00 Bits Name 15-14 NErle 13-12 NFNse 11-10 RHDet Rx Half-Duplex Detection Threshold 9-8 HDly 7-6 NseRmp Background Power Estimator Ramp Rate 5-4 RSThd 3 PCSen * Denotes reset ...
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RHDet - Receive Half-Duplex Detection Threshold The sensitivity of the speech detector controls channel switching and ownership in half-duplex mode. The receive speech detector registers speech if the receive channel signal power is RHDet above the noise floor for the ...
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Register 3 b15 b14 b13 b12 b11 AErle AFNse THDet 00 00 Bits Name 15-14 AErle 13-12 AFNse AEC Full-Duplex Noise Threshold 11-10 THDet Tx Half-Duplex Detection Threshold 9-8 TSAtt 7-6 TSBias 5-4 TSThd 3 HHold * Denotes reset value ...
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Threshold The sensitivity of the speech detector controls channel switching and ownership in half-duplex mode. The transmit speech detector registers speech if the transmit channel signal power is TH- Det above the noise floor of the transmit channel. TSAtt - ...
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Alternatively, the CLKI pin may be driven by a CMOS level clock signal. The clock may vary from 20.480 ...
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Noise and Grounding Since the CS6420 is a mixed-signal integrated cir- cuit, the system designer must pay special attention to layout and decoupling to minimize noise con- cerns. The three best methods to reduce noise when using the CS6420 are ...
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DESIGN CONSIDERATIONS When designing the CS6420 into a system im- portant to keep several considerations in mind. These concerns can be loosely grouped into three categories: algorithmic considerations, circuit de- sign considerations, and system design consider- ations. Algorithmic ...
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The worst case situation for the CS6420 is when parties at both ends are speaking and the person at the near-end is moving. In this case, the echo can- celler will ...
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If beta is too low, the adap- tive filter will be slow to adapt. Conversely too high, the filter will be unstable and will create unwanted noise in the system. In most echo canceller ...
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The CS6420 implements a half-duplex mode to guarantee communication even when the echo canceller is disabled. When the CS6420 is first powered on, or emerges from a reset, the echo canceller coefficients are cleared, and the echo cancellers ...
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Fs 0dB -30dB (a) Input Signal Fs 0dB -30dB (d) Input Signal transmit channel will engage extra attenuation whenever only the far-end talker is speaking. How- ever, if the near-end talker starts speaking, the at- tenuation is removed and the ...
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We recommend using larger values of TSBias relative to TSThd settings in or- der to facilitate ease of near-end speech transmis- sion. For example, the default setting for TSThd and 18 dB for TSBias. ...
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The three pins that comprise the Microcontroller Interface are STROBE, DATA, and DRDY. STROBE must not exceed the system clock of the CS6420 in speed. Also, four extra clocks are re- quired after DRDY is brought high in order to ...
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The basic constraint on getting good echo canceller performance is that the maximum output should not clip when coupled to the input. For example speakerphone, AO provides 1 V er, the reflections reaching the microphone should present ...
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Convergence Time Convergence time is a measure of how quickly the adaptive filter can model the echo path. From cleared coefficients, the training signal is injected into the echo canceller and the time for the ERLE to reach a given ...
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PIN DESCRIPTIONS AVDD AGND DRDY STROBE Analog Interface AO - Acoustic Interface Output, Pin 3 Analog voltage output for the acoustic side (near-end output/receive output). Maximum output signal (2.8 V rms speaker driver. The output is pre-compensated ...
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NI - Network Interface Input, Pin 17 Input to the network side analog-to-digital converter (far-end input/receive input). This input expects a single-pole RC anti-aliasing filter with a corner frequency of 8 kHz. Maximum signal level before clipping at this point ...
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Miscellaneous NC1 - No Connect, Pin 9 Must be floating for normal operation. NC2 - No Connect, Pin 10 Must be floating for normal operation. NC3 - No Connect, Pin 11 Must be floating for normal operation. NC4 - No ...
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GLOSSARY Echo A signal that returns to its source after some delay. Network Echo Echo resulting from signal reflection due to an impedance mismatch in a 2-to-4 wire converter (hybrid). Acoustic Echo Echo created by signal propagation in a room ...
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Howling In full-duplex operation, both the microphone and speaker are active at the same time, which, in conjunction with the reflection off the hybrid, creates a closed loop. The signal coupling between the speaker and the microphone can cause feedback ...
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Coverage Time The CS6420 echo canceller has 508 taps and it can sample an analog signal kHz rate. 512 x 1/8kHz = 63.5 ms. Sound travels through air at a rate of around 1 ft/ms. Thus the ...
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PACKAGE DIMENSIONS DS205PP2 20-Pin SOIC MILLIMETERS DIM MIN NOM MAX MIN A 2.41 2.54 2.67 0.095 A 0.127 - 0.300 0.005 2.29 2.41 2.54 ...
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Notes • ...
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... P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Description The CDB6420 allows an end-user to quickly and easily integrate the CS6420 Full-Duplex Speakerphone IC into a system and evaluate its performance. comes with software which allows the registers of the CS6420 to be manipulated from a personal computer running Windows ...
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... Maximum Analog Input Level (APO, NI) Maximum Analog Output Level (AO, NO) Input and Output Offset Voltage Maximum Speaker Output Voltage 1. Assumes TGain=RGain= 0 dB. 40 Symbol Min Typ +5VA 4.5 5 AOp V Note 1 2 2.8 out V 2.12 off V 6.4 spkr CDB6420 Max Units 5 ° VDC V pp DS205DB1 ...
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... V full-scale. pp CS6420 The heart of the CDB6420, the CS6420 Full-Du- plex Speakerphone Chip, is shown in Figure 5. The outputs AO and NO are shown with the output low- pass filters that remove the high frequency compo- nents from the delta-sigma DACs. The inputs APO_IN and NI are shown with the anti-aliasing network they require ...
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... Figure 3. Microphone Input Circuit Figure 4. Speaker Output Circuit CDB6420 DS205DB1 ...
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... TGain (see the Software section) set to 0 dB. Parallel Port Interface Figure 6 shows the parallel port interface of the CDB6420 that connects to a PC’s parallel port. The 74HCT541 buffer serves to protect the CS6420 from any damaging surges. The buffer is socketed for easy replacement. Four of the parallel port data lines are used to control the microcontroller interface pins of the CS6420 ...
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... Figure 6. Parallel Port press the Current Reset Option button. If you have an ammeter on the power supply to the CDB6420, you will see a dramatic decrease in current con- sumption. Alternatively, you can probe the RST line and you should see it go low when you press the button ...
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... Main Window Figure 9 shows the main window of the CDB6420 Control Program. The main window is a block di- agram representation of the internals of the CS6420 with all the registers placed in their appropriate lo- cations in the signal flow ...
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... Please carefully read the Register section of that document for full details. RGain - Receive ADC Analog Gain 0 dB, 6 dB, 9.5 dB, 12 dB: set gain of the ADC at NI RSD - Receive Suppression Disable checked: disable receive suppression unchecked: enable receive suppression Figure 9. Main Control Panel CDB6420 DS205DB1 ...
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... Clear: coefficients held to zero (no cancellation) Freeze: coefficients held to current values and adapta- tion halted AErle - Acoustic ERLE threshold 24 dB: default 18 dB: acoustic echo canceller tends full-du- plex more easily (faster) 30 dB: acoustic echo canceller requires good perfor- mance full-duplex (slower) CDB6420 47 ...
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... Power Down: hold CS6420 RST low to force low power mode Power Up, Cold Reset, Current: bring CS6420 RST high; restore register values indicated by controls Power Up, Warm Reset, Current: bring CS6420 RST high; warm reset and re- store register values indicated by controls CDB6420 DS205DB1 ...
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... DS205DB1 CDB6420 49 ...
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... CDB6420 DS205DB1 ...
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... DS205DB1 CDB6420 51 ...
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