EVAL-ADUC812QSZ Analog Devices Inc, EVAL-ADUC812QSZ Datasheet - Page 13

• Manufacturer Part Number: EVAL-ADUC812QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC812QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC812
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC812
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. E
ADCCON1—(ADC Control SFR #1)
The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as
detailed below.
SFR Address
SFR Power-On Default Value
Bit
ADCCON1.7 MD1
ADCCON1.6 MD0
ADCCON1.5 CK1
ADCCON1.4 CK0
ADCCON1.3 AQ1
ADCCON1.2 AQ0
ADCCON1.1 T2C
ADCCON1.0 EXC
M
D
1
Name
M
D
0
Description
The mode bits (MD1, MD0) select the active operating mode of the ADC as follows:
MD1 MD0 Active Mode
ADC clock. A typical ADC conversion will require 17 ADC clocks. The divider ratio is selected
The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold
amplifier to acquire the input signal, and are selected as follows:
The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit be used as
The external trigger enable bit (EXC) is set by the user to allow the external CONVST pin to be
0
0
1
1
Note: In power-down mode the ADC V
powered down, thus minimizing current consumption.
The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the
as follows:
CK1 CK0 MCLK Divider
0
0
1
1
AQ1 AQ0 #ADC Clks
0
0
1
1
the ADC convert start trigger input. ADC conversions are initiated on the second Timer 2 overflow.
used as the active low convert start input. This input should be an active low pulse (minimum
pulsewidth >100 ns) at the required sample rate.
EFH
20H
C
0
1
0
1
0
1
0
1
0
1
0
1
K
1
Table III. ADCCON1 SFR Bit Designations
ADC powered down
ADC normal mode
ADC powered down if not executing a conversion cycle
ADC standby if not executing a conversion cycle
1
2
4
8
1
2
4
8
C
K
0
–13–
REF
A
Q
circuits are maintained on, whereas all ADC peripherals are
1
A
Q
0
T
2
C
ADuC812
E
X
C