ADD-FLOATALL Altera, ADD-FLOATALL Datasheet - Page 28
ADD-FLOATALL
Manufacturer Part Number
ADD-FLOATALL
Description
Quartus II Software Additional Floating-node Seat
Manufacturer
Altera
Series
QUARTUS IIr
Datasheet
1.DK-START-3C25N.pdf
(74 pages)
Specifications of ADD-FLOATALL
Supported Families
Quartus II
Supported Hosts
Windows, Linux, UNIX
License Type
Networked
Tool Function
Compiler
Supported Devices
Cyclone IV
Lead Free Status / RoHS Status
na
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Devices
Cyclone V GX FPGA Features
26
LEs
M10K memory blocks (Kb)
MLAB
PLLs
Global clock networks
DSP blocks
PCIe hard IP blocks
Memory controllers
I/O voltage levels
supported (V)
I/O standards supported
LVDS channels (875 Mbps
receive, 840 Mbps transmit)
Transceiver (SERDES)
channels
Memory devices supported
Altera Product Catalog
•
2011
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15, Differential SSTL-18, Differential
•
www.altera.com
SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential HSTL-18, SSTL-15 (I and II), SSTL-18 (I and II),
5CGXC3
SSTL-2 (I and II), 1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II), HiSpi, SLVS, Sub-LVDS
25,000
1,200
16
40
48
5
1
1
3
Cyclone V GX FPGAs (1.1 V), 3.125-Gbps Transceivers
5CGXC4
50,000
2,920
100
16
70
6
1
2
6
25% of ALMs can be configured as MLABs
DDR3, DDR2, DDR, LPDDR, LPDDR2
1.1, 1.2, 1.5, 1.8, 2.5, 3.3
5CGXC5
75,000
4,620
132
100
16
6
1
2
6
5CGXC7
150,000
6,160
220
122
16
7
1
2
9
5CGXC9
300,000
12,760
406
122
16
12
8
1
2
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