PN5120A0HN1/C2,118 NXP Semiconductors, PN5120A0HN1/C2,118 Datasheet - Page 79
PN5120A0HN1/C2,118
Manufacturer Part Number
PN5120A0HN1/C2,118
Description
IC TRANSMISSION MOD 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.PN5120A0HN1C2118.pdf
(125 pages)
Specifications of PN5120A0HN1/C2,118
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
11.2 Separated Read/Write strobe
11.3 Common Read/Write strobe
For timing requirements refer to
For timing requirements refer to
Fig 25. Connection to host controller with separated Read/Write strobes
Fig 26. Connection to host controller with common Read/Write strobes
non multiplexed
address
low
low
low
high
high
high
multiplexed address/data AD0...AD7)
address latch enable (ALE)
not read strobe (NRD)
not write (NWR)
remark: *depending on the package type.
non multiplexed
address
low
low
low
high
high
low
multiplexed address/data AD0...AD7)
address strobe (AS)
not data strobe (NDS)
read not write (RD/NWR)
remark: *depending on the package type.
All information provided in this document is subject to legal disclaimers.
DECODER
DECODER
ADDRESS
ADDRESS
Rev. 3.6 — 10 March 2011
111336
NCS
A5*
A4*
A3
A2
A1
A0
D0...D7
ALE
NRD
NWR
NCS
A5*
A4*
A3
A2
A1
A0
D0...D7
ALE
NRD
NWR
Section 25.2 “8-bit parallel interface
Section 25.2 “8-bit parallel interface timing”
PN512
PN512
address bus
address bus (A0...A3[A5*])
data bus (D0...D7)
high
not data strobe (NRD)
not write (NWR)
address bus
address bus (A0...A3[A5*])
Data bus (D0...D7)
high
not data strobe (NDS)
read not write (RD/NWR)
DECODER
DECODER
ADDRESS
ADDRESS
Transmission module
timing”.
© NXP B.V. 2011. All rights reserved.
NCS
A0...A3[A5*]
D0...D7
ALE
NRD
NWR
NCS
A0...A3[A5*]
D0...D7
ALE
NRD
NWR
PN512
PN512
PN512
001aan223
001aan224
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