PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 66
PN5120A0HN1/C2,151
Manufacturer Part Number
PN5120A0HN1/C2,151
Description
IC TRANSMISSION MOD 32-HVQFN
Manufacturer
NXP Semiconductors
Specifications of PN5120A0HN1/C2,151
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PN5120A0HN1/C2,151
Manufacturer:
NXP/恩智浦
Quantity:
20 000
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NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
10.2.1 SPI read data
10.2.2 SPI write data
10.2 Serial Peripheral Interface
A serial peripheral interface (SPI compatible) is supported to enable high-speed
communication to the host. The interface can handle data speeds up to 10 Mbit/s. When
communicating with a host, the PN512 acts as a slave, receiving data from the external
host for register settings, sending and receiving data relevant for RF interface
communication.
An interface compatible with SPI enables high-speed serial communication between the
PN512 and a microcontroller. The implemented interface is in accordance with the SPI
standard.
The timing specification is given in
The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be
generated by the master. Data communication from the master to the slave uses the
MOSI line. The MISO line is used to send data from the PN512 to the master.
Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI
and MISO lines must be stable on the rising edge of the clock and can be changed on the
falling edge. Data is provided by the PN512 on the falling clock edge and is stable during
the rising clock edge.
Reading data using SPI requires the byte order shown in
possible to read out up to n-data bytes.
The first byte sent defines both the mode and the address.
Table 142. MOSI and MISO byte order
[1]
Remark: The MSB must be sent first.
To write data to the PN512 using SPI requires the byte order shown in
possible to write up to n data bytes by only sending one address byte.
Line
MOSI
MISO
Fig 12. SPI connection to host
X = Do not care.
Byte 0
address 0
X
[1]
All information provided in this document is subject to legal disclaimers.
Rev. 3.6 — 10 March 2011
Byte 1
address 1
data 0
111336
SCK
MOSI
MISO
NSS
Section 25.1 on page
Byte 2
address 2
data 1
SCK
MOSI
MISO
NSS
PN512
To
...
...
001aan220
107.
Table 142
Byte n
address n
data n − 1
Transmission module
to be used. It is
Table
© NXP B.V. 2011. All rights reserved.
PN512
143. It is
Byte n + 1
00
data n
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