DS3994Z+W Maxim Integrated Products, DS3994Z+W Datasheet - Page 12

• Manufacturer Part Number: DS3994Z+W
• Description: Display Drivers 4-Ch Cold-Cathode Fl uorescent Controller
• Manufacturer: Maxim Integrated Products

Specifications of DS3994Z+W

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If a BDS_Delay is used that is longer than the burst peri-
od, then the gate drivers, GA and GB, have no output.
For example, assume a lamp frequency of 50kHz and a
burst frequency of 167Hz. The step resolution of the
burst-dimming stagger would be 40µs (2/50,000). To
achieve equal stagger, as shown in Figure 5, the
BDS1/2/3/4 registers would be programmed as
described in Table 3.
4-Channel Cold-Cathode
Fluorescent Lamp Controller
When the DPWM signal is provided by an external
source, either from the PSYNC pin of another DS3994 or
from some other user-generated source, it is input into the
PSYNC I/O pin of the DS3994. In this mode, the BRIGHT
and POSC inputs are disabled and should be grounded
(see Figure 4). When multiple DS3994s are used in a
design, DS3994s configured to use externally generated
DPWM signals are referred to as DPWM receivers.
Table 2. Multiplication Factor M, Based on Lamp Frequency Oscillator and DPWM
Frequency Oscillator
Table 3. Example BDS1/2/3/4 Programmed Values
12
CHANNEL
POSCR1
(CR2.2)
____________________________________________________________________
0
0
1
1
1
2
3
4
BDS_Resolution
REGISTER
POSCR0
(CR2.1)
BDS1
BDS2
BDS3
BDS4
0
1
0
1
OSCILLATOR RANGE (Hz)
DESIRED STAGGER (ms)
=
SELECTED PWM
f
LF : OSC
180 to 440
22.5 to 55
45 to 110
90 to 220
M
1.5
3.0
4.5
0
STEP RESOLUTION (µs)
LAMP OSCILLATOR = 40
TO 80kHz (LOFS = 0)
M, LAMP CYCLE PERIOD MULTIPLICATION FACTOR
BDS_Delay = BDS_Resolution x BDS_8-Bit_Value
The DS3994 also features burst dimming stagger (BDS)
functionality integrated into the burst dimming con-
troller. BDS is useful to reduce the current ripple on the
DC supply as well as improve the visual motion
response of the LCD panel. This feature allows users to
enter a digital code into each channel independent
register (BDS1/2/3/4) that would delay the start of each
burst period. The 8-bit BDS code can be calculated by
using Table 2 and the following equations.
Figure 5. Example Burst Dimming Stagger Cycle
Burst Dimming Stagger (BDS) Functionality
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
40
40
40
40
8
4
2
1
1.5ms
BURST DIMMING CYCLE (167Hz/6ms)
COUNT
113
38
75
0
3.0ms
LAMP OSCILLATOR = 20
TO 40kHz (LOFS = 1)
PROGRAMMED VALUE
4.5ms
8
4
2
1
4Bh
00h
26h
71h