S1D13515F00A100 Epson, S1D13515F00A100 Datasheet - Page 7

• Manufacturer Part Number: S1D13515F00A100
• Description: Display Drivers LCD Controller 256QFP22
• Manufacturer: Epson

Specifications of S1D13515F00A100

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.1.2 S2D13515 Register Settings for Sharp LQ043xxx, 480x272 TFT Panel
The registers listed below are only those associated with panel specific timing issues. All other registers are not
shown here.
The above values are intended as examples. This example assumes that CLKI = 20MHz and that the PLL2 is used
to generate LCDCLK. Actual settings can vary and still remain within the LCD panel timing requirements.
S2D13515
Interfacing the Sharp LQ043xxx 480x272 TFT Panel (Rev. 0.01)
REG[402Ah]
REG[402Bh]
REG[402Ch]
REG[402Dh]
REG[402Eh]
REG[0031h]
REG[4000h]
REG[4001h]
REG[4020h]
REG[4022h]
REG[4023h]
REG[4024h]
REG[4025h]
REG[4026h]
REG[4027h]
REG[4028h]
REG[4029h]
REG[402Fh]
REG[4030h]
REG[4031h]
REG[4032h]
REG[4033h]
REG[4070h]
REG[4021h
Register
Table 1-2: Example Register Settings for Sharp LQ043xxx 480x272 TFT Panel
Value
BXh
0Ch
EFh
1Dh
0Ch
31h
0Xh
02h
2Ah
00h
28h
00h
00h
00h
01h
0Fh
01h
00h
09h
00h
00h
00h
01h
00
set LCD2PCLK divide, LCD2PCLK = 8MHz
assuming LCDCLK=80MHz
LCD2 RGB8:8:8), generic RGB
Display data is latched on falling edge of PCLK, 24-bit panel
Hsync period = 525 pixels
horizontal display period = 480 pixels
horizontal display period start position = 43 pixels
Hsync width = 41 pixels, active low pulse
Hsync start position = 0 pixels
Vsync period = 286 lines
vertical display period = 272 lines
vertical display period start position = 12 lines
Vsync width = 10 lines
Vsync active low
Vsync start position = 0 lines
enable LCD2 output
EPSON
Chapter 1 Interfacing the Sharp LQ043xxx 480x272 TFT Panel
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