CYII4SM014KAA-GECH Cypress Semiconductor Corp, CYII4SM014KAA-GECH Datasheet - Page 16

• Manufacturer Part Number: CYII4SM014KAA-GECH
• Description: Optical Sensors - Board Mount 50mA 3.3V CMOS Sense
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYII4SM014KAA-GECH

• Supply Current: 50 mA
• Operating Supply Voltage: 3.3 V
• Package / Case: PGA-49
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7. Pinout Configuration (continued)
Document #: 38-05709 Rev. *F
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Pin #
CLK_YL
VDDR
VDD
GND
GNDAB
SELECT
RESET
CBIAS
PCBIAS
DIN
SCLK
CS
PC
SYNC_X
GND
VDD
CLK_X
SHR
SHS
XBIAS
ABIAS
Name
Clock of YL shift register
Power supply for reset line drivers
Power supply
Ground
Anti-blooming reference level (pin 33)
Control select line of pixel array
Reset of the selected row of pixels
Bias current column amplifiers
Bias current
Serial data input
SPI interface clock
Chip select
Row initialization pulse
Sets the X-shift register to row 1
Ground
Power supply
Clock of YR shift register
Row track and hold reset level
(1 = hold; 0 = track).
Row track and hold signal level (1 = hold;
0 = track)
Bias current X multiplexer
Bias current pixel array
Function
High active. See timing diagrams
Shifts on rising edge
Nominal 4 V
Connected on-chip to pin 21
Nominal 3.3 V
0 V
Typ. 0 V. Set to 1 V for improved anti-blooming
High active. See timing diagrams
Connect with 22 k  to V
Connect with 22 k  to V
16-bit word. LSB first
Shifts on rising edge
Data copied to registers on rising edge
See timing diagrams
Low active. Synchronous sync on rising edge of CLK_X
150 ns setup time
0 V
Nominal 3.3 V
Shifts on rising edge
See timing diagram
See timing diagram
Connect with 10 k  to V
Connect with 10 M  to V
DD
DD
DD
DD
Comment
and decouple with 100 nF to GND
and decouple with 100 nF to GND
and decouple with 100 nF to GND
and decouple with 100 nF to GND
CYII4SM014KAA
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