CPC7593BBTR Clare, CPC7593BBTR Datasheet - Page 18

• Manufacturer Part Number: CPC7593BBTR
• Description: Solid State Relays 10-pole, no SCR, SOIC LCAS, T/R
• Manufacturer: Clare

Specifications of CPC7593BBTR

• Relay Type: Line Card
• Package / Case: SOIC 28

CPC7593
As shown in the table
Logic Table (Ringing to Talk Transition)” on page
operation is similar to the one shown in
Break-Before-Make Operation Logic Table (Ringing to Talk
Transition)” on page
select the all-off state and when the IN
IN
talk state.
1. Pull T
2. Keep T
2.4 Data Latch
The CPC7593 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch are via the input pins, while the output of the data
latch are internal nodes used for state control. When
the LATCH enable control pin is at logic 0 the data
latch is transparent and the input data control signals
flow directly through the latch to the state control
circuitry. A change in input will be reflected by a
change in switch state. Whenever the LATCH enable
control pin is at logic 1, the latch is active and data is
locked. Subsequent input changes will not result in a
change to the control logic or affect the existing switch
state.
18
Ringing
Before-
Break-
State
All-off
Make
TESTin
Talk
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
2.3.8 Alternate Break-Before-Make Operation Logic Table (Ringing to Talk Transition)
and IN
IN
SD
SD
RINGING
1
1
0
0
to a logic low to end the ringing state.
low for at least one-half the duration of
TESTout
18, except in the method used to
IN
TESTin
“Break-Before-Make Operation
0
0
0
0
inputs are reconfigured for the
IN
TESTout
0
1
0
0
RINGING
Latch
“Alternate
X
0
0
17, this
,
T
Z
0
Z
www.clare.com
SD
SW4 waiting for zero current
Zero current has occurred.
Hold this state for at least
one-half of ringing cycle.
Break switches close.
SW4 has opened
3. During the T
4. Release T
When using T
states are “0” which over rides logic input pins and
forces an all-off state and “Z” which allows switch
control via the logic input pins. This requires the use of
an open-collector or open-drain type buffer.
Switches will remain in the state they were in when the
LATCH pin changes from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. However, neither the T
output control functions are affected by the latch
function. Internal thermal shutdown control and
external “All-off” control via T
state of the LATCH enable input.
2.5 T
The T
internal pull up sourced from V
pin indicates the status of the thermal shutdown
circuitry. Typically, during normal operation, this pin will
be pulled up to V
create excess thermal loading the CPC7593 will enter
thermal shutdown and a logic low will be output.
to turn off.
Timing
circuit to enter the break before make state.
IN
(0,0,0).
activate the break switches.
-
SD
SD
TESTin
Pin Description
pin is a bi-directional I/O structure with an
and IN
SD
SD
SD
DD
as an input, the two recommended
allowing the internal pull-up to
Switches
Break
TESTout
low period, set the IN
but under fault conditions that
Off
Off
Off
On
inputs to the talk state
Ringing
Return
Switch
(SW3)
SD
On
Off
Off
Off
SD
DD
is not affected by the
. As an output, this
input nor the T
Ringing
Switch
(SW4)
On
On
Off
Off
RINGING
Switches
Test
SD
Off
Off
Off
Off
,
R04