CDB5374 Cirrus Logic Inc, CDB5374 Datasheet - Page 22

• Manufacturer Part Number: CDB5374
• Description: Audio Modules & Development Tools 2-Ch DS Modulator & Hydrophone Demo Brd
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5374

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.3.1.1
The CS5376A digital filter creates the analog sampling clock used by the CS5374 ∆Σ modulators and
CS4373A test DAC (MCLK). This clock has strict jitter requirements to guarantee the accuracy of analog-
to-digital and digital-to-analog conversion, and so is carefully routed between the digital filter and modu-
lators/test DAC.
2.3.1.2
Configuration of the CS5376A digital filter is through the SPI 1 port by the on-board 8051 microcontroller,
which receives commands from the PC evaluation software via the USB interface. Evaluation software
commands can write/read digital filter registers, specify digital filter coefficients and test bit stream data,
and start/stop digital filter operation. Alternately, the digital filter can automatically load configuration in-
formation from an on-board serial EEPROM.
Configuration of the digital filter is selected by the BOOT signal from dip switch #1 (S5, #1). By default the
BOOT signal is set low (S5, #1 - LO) to indicate configuration information is written by the microcontroller.
If BOOT is set high (S5, #1 - HI), the digital filter attempts to automatically read configuration information
from the serial EEPROM after reset.
2.3.2
A Xilinx CPLD is included on CDB5374 (XCR3128XL-10VQ100I) as an interface between the CS5376A
digital filter and the microcontroller. By default the CPLD only passes through the interface signals, but
can be reprogrammed to disconnect the on-board 8051 microcontroller and connect to another external
microcontroller through the spare dual-row headers. Control signals taken off the CDB5374 board to an
external microcontroller should pair with a ground return wire to maintain signal integrity.
Free software tools and an inexpensive hardware programmer for the Xilinx CPLD are available from the
internet (http://www.xilinx.com). The hardware programmer interfaces with the Xilinx JTAG programming
port (J39) on CDB5374. Note that early versions of the Xilinx WebPack tools (7.1i SP1 and earlier) have
a bug in the JEDEC programming file for the CPLD included on CDB5374, and WebPack version 7.1i SP2
or later is required.
Included below is the default Verilog HDL file used by CDB5374 inside the interface CPLD. Comparing
the input and output definitions of this file with the CPLD schematic pinout should demonstrate how sig-
nals are selected and passed through from the microcontroller to the CS5374A digital filter. Several signal
connections to the CPLD are not defined in the default HDL file, but are routed to the CPLD on CDB5374
for convenience during custom reprogramming.
22
Interface CPLD
MCLK Conversion to ACLK
Configuration - SPI1 Port
CDB5374
DS862DB1